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    Method and apparatus for automatic recovery from a failed node concurrent maintenance operation
    2.
    发明授权
    Method and apparatus for automatic recovery from a failed node concurrent maintenance operation 失效
    从失败的节点并发维护操作中自动恢复的方法和装置

    公开(公告)号：US07453816B2

    公开(公告)日：2008-11-18

    申请号：US11054288

    申请日：2005-02-09

    申请人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

    发明人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

    IPC分类号： G01R31/08 ,  G06F13/00

    CPC分类号： G06F11/0793 ,  G06F11/0724

    摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed.If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

    摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

    Power-efficient thread priority enablement
    5.
    发明授权
    Power-efficient thread priority enablement 有权
    高效的线程优先级启用

    公开(公告)号：US08261276B2

    公开(公告)日：2012-09-04

    申请号：US12059576

    申请日：2008-03-31

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

    IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F13/28 ,  G06F1/32

    CPC分类号： G06F9/4893 ,  Y02D10/24

    摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

    摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

    Synchronizing triggering of multiple hardware trace facilities using an existing system bus
    6.
    发明授权
    Synchronizing triggering of multiple hardware trace facilities using an existing system bus 失效
    使用现有系统总线同步触发多个硬件跟踪工具

    公开(公告)号：US07979750B2

    公开(公告)日：2011-07-12

    申请号：US12144422

    申请日：2008-06-23

    申请人： Ra'ed Mohammad Al-Omari ,  Michael Stephen Floyd ,  Paul Frank Lecocq

    发明人： Ra'ed Mohammad Al-Omari ,  Michael Stephen Floyd ,  Paul Frank Lecocq

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2268 ,  G06F11/348

    摘要： A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.

    摘要翻译： 在用于使用现有总线触发多个硬件跟踪设备的数据处理系统中公开了一种方法，装置和计算机程序产品。 多个硬件跟踪设备包括第一个硬件跟踪设备和第二个硬件跟踪设备。 数据处理系统包括第一处理器，其包括第一硬件跟踪设备和利用系统总线耦合在一起的第一处理单元，以及包括第二硬件跟踪设备的第二处理器和利用系统耦合在一起的第二处理单元 总线。 当处理器处于正常的非跟踪模式时，利用系统总线在第一和第二处理单元之间传送信息，其中信息根据标准系统总线协议被格式化。 触发事件使用相同的标准系统总线传输到硬件跟踪设备，触发事件也根据标准系统总线协议进行格式化。

    Method of seamlessly integrating thermal event information data with performance monitor data
    7.
    发明授权
    Method of seamlessly integrating thermal event information data with performance monitor data 有权
    将热事件信息数据与性能监视数据无缝集成的方法

    公开(公告)号：US07472315B2

    公开(公告)日：2008-12-30

    申请号：US11054292

    申请日：2005-02-09

    申请人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    发明人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00

    摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.

    摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

    INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING
    8.
    发明申请
    INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING 有权
    智能SMT螺纹连接检测进入帐户共享资源内容/阻塞

    公开(公告)号：US20080141000A1

    公开(公告)日：2008-06-12

    申请号：US12033385

    申请日：2008-02-19

    申请人： Michael Stephen Floyd ,  Larry Scott Leitner

    发明人： Michael Stephen Floyd ,  Larry Scott Leitner

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

    摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

    摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

    Accessing and manipulating microprocessor state
    9.
    发明授权
    Accessing and manipulating microprocessor state 失效
    访问和操作微处理器状态

    公开(公告)号：US07305586B2

    公开(公告)日：2007-12-04

    申请号：US10424485

    申请日：2003-04-25

    申请人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

    发明人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2236

    摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.

    摘要翻译： 微处理器包括外部可访问端口和连接到端口的串行通信总线。 处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。 该卫星使外部代理可以通过串行总线直接向管线提供指令。 专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。 在执行指令期间，执行流水线可以访问专用寄存器。 以这种方式，卫星电路使外部代理能够访问架构状态。 当处理器的系统时钟保持有效时，通信总线可以访问卫星。 在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。

    Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components
    10.
    发明授权
    Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components 有权
    动态，非侵入式检测热插拔问题组件，并从问题组件重新分配系统资源

    公开(公告)号：US07117388B2

    公开(公告)日：2006-10-03

    申请号：US10424278

    申请日：2003-04-28

    申请人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    发明人： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2043 ,  G06F11/2028 ,  G06F11/2289

    摘要： A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

    摘要翻译： 一种用于动态检测热插拔处理系统中的问题组件的方法，系统和数据处理系统，并且通过热删除方法自动移除问题组件，而不会中断整个系统的处理。 提供无中断的热插拔功能的数据处理系统设计有一个额外的逻辑，用于启动和/或完成热插拔组件上的一系列工厂级测试，以确定组件是否正常工作。 当组件运行不正常时，操作系统将组件的工作负载重新分配给其他组件，以便系统，并且当操作系统完成重新分配时，服务组件启动组件的热删除，以使组件 与系统逻辑和电气分离。