利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

104 条记录 (耗时 0.026 秒)

    Method and system for providing a contact on a semiconductor device
    1.
    发明授权
    Method and system for providing a contact on a semiconductor device 失效
    用于在半导体器件上提供接触的方法和系统

    公开(公告)号：US6103593A

    公开(公告)日：2000-08-15

    申请号：US23836

    申请日：1998-02-13

    申请人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    发明人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76237 ,  H01L21/76834 ,  Y10S438/97

    摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

    摘要翻译： 公开了一种在半导体上提供至少一个接触的方法。 半导体包括多个隔离结构。 该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。 在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。

    Shallow trench isolation filled with thermal oxide
    2.
    发明授权
    Shallow trench isolation filled with thermal oxide 失效
    浅沟隔离填充热氧化物

    公开(公告)号：US06232646B1

    公开(公告)日：2001-05-15

    申请号：US09082607

    申请日：1998-05-20

    申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    IPC分类号： H01L2900

    CPC分类号： H01L21/7621 ,  H01L21/76232

    摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

    摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
    4.
    发明授权
    System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
    用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法

    公开(公告)号：US08759894B1

    公开(公告)日：2014-06-24

    申请号：US11189765

    申请日：2005-07-27

    申请人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    发明人： Yider Wu ,  Hiroyuki Ogawa ,  Unsoon Kim ,  Angela T. Hui

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/66833

    摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

    摘要翻译： 提供了包括基板的存储器件。 第一电介质层形成在衬底上。 在衬底和第一介电层的一部分中形成隔离沟槽。 在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。 在所述至少两个电荷存储元件上形成第二电介质层。 控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度 所述至少两个电荷存储元件和所述控制栅极层。

    Method for producing a shallow trench isolation filled with thermal oxide
    5.
    发明授权
    Method for producing a shallow trench isolation filled with thermal oxide 有权
    用于生产填充有热氧化物的浅沟槽隔离体的方法

    公开(公告)号：US06444539B1

    公开(公告)日：2002-09-03

    申请号：US09784892

    申请日：2001-02-15

    申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

    IPC分类号： H01L2176

    CPC分类号： H01L21/7621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

    摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

    摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
    6.
    发明授权
    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
    非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间

    公开(公告)号：US06664191B1

    公开(公告)日：2003-12-16

    申请号：US09973131

    申请日：2001-10-09

    申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    IPC分类号： H01L21302

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

    摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

    摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

    System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device
    10.
    发明授权
    System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device 有权
    用于改善半导体器件中的氧化物 - 氧化物 - 氧化物（ONO）耦合的系统和方法

    公开(公告)号：US07679129B1

    公开(公告)日：2010-03-16

    申请号：US11128389

    申请日：2005-05-13

    申请人： Angela T. Hui ,  Unsoon Kim ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    发明人： Angela T. Hui ,  Unsoon Kim ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

    摘要： A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.

    摘要翻译： 存储器件包括衬底和形成在衬底上的第一电介质层。 在第一电介质层上形成至少两个电荷存储元件。 衬底和第一介电层包括填充有氧化物材料的浅沟槽。 形成在浅沟槽的中心部分的氧化物材料被去除以提供具有基本上矩形横截面的区域。