摘要:
A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.
摘要:
The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要:
The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semiconductor devices.
摘要:
The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semiconductor devices.
摘要:
The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要:
A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要:
A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要:
A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要:
A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要:
Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.