公开(公告)号：US20070281469A1

公开(公告)日：2007-12-06

申请号：US11839258

申请日：2007-08-15

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US20060081986A1

公开(公告)日：2006-04-20

申请号：US10964882

申请日：2004-10-14

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US20080220608A1

公开(公告)日：2008-09-11

申请号：US12121216

申请日：2008-05-15

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US07282802B2

公开(公告)日：2007-10-16

申请号：US10964882

申请日：2004-10-14

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US07906428B2

公开(公告)日：2011-03-15

申请号：US12121216

申请日：2008-05-15

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US07528065B2

公开(公告)日：2009-05-05

申请号：US11333068

申请日：2006-01-17

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

公开(公告)号：US07105445B2

公开(公告)日：2006-09-12

申请号：US11034890

申请日：2005-01-14

申请人： Kwong-Hon Wong ,  Louis C. Hsu ,  Timothy J. Dalton ,  Carl J. Radens ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Theodorus E. Standaert

发明人： Kwong-Hon Wong ,  Louis C. Hsu ,  Timothy J. Dalton ,  Carl J. Radens ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Theodorus E. Standaert

IPC分类号： H01L21/44

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连的方法，其包括在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸，并且在所述互连结构的所述延伸部分上沉积包封盖 。

公开(公告)号：US06709562B1

公开(公告)日：2004-03-23

申请号：US09348632

申请日：1999-07-06

申请人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

IPC分类号： C25D712

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/123 ,  H01L21/76877

摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US06946716B2

公开(公告)日：2005-09-20

申请号：US10773434

申请日：2004-02-09

申请人： Panayotis Constantinou Andricacos ,  Harikilia Deligianni ,  John Owen Dukovic ,  Daniel C. Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth P. Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Constantinou Andricacos ,  Harikilia Deligianni ,  John Owen Dukovic ,  Daniel C. Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth P. Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L29/00

CPC分类号： C25D3/38 ,  C25D5/022 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76885

摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US5516412A

公开(公告)日：1996-05-14

申请号：US441853

申请日：1995-05-16

申请人： Panayotis C. Andricacos ,  Kirk G. Berridge ,  John O. Dukovic ,  Matteo Flotta ,  Jose Ordonez ,  Helmut R. Poweleit ,  Jeffrey S. Richter ,  Lubomyr T. Romankiw ,  Otto P. Schick ,  Frank Spera ,  Kwong-Hon Wong

发明人： Panayotis C. Andricacos ,  Kirk G. Berridge ,  John O. Dukovic ,  Matteo Flotta ,  Jose Ordonez ,  Helmut R. Poweleit ,  Jeffrey S. Richter ,  Lubomyr T. Romankiw ,  Otto P. Schick ,  Frank Spera ,  Kwong-Hon Wong

IPC分类号： C25D17/00 ,  C25D21/10 ,  C25F7/00 ,  C25D17/06

CPC分类号： C25D17/001 ,  C25D17/00 ,  C25D17/007 ,  C25D17/02 ,  C25D17/08 ,  C25D21/10 ,  C25F7/00 ,  Y10S204/07

摘要： An electroplating cell includes a floor, ceiling, front wall, and back wall forming a box having first and second opposite open ends. A rack for supporting an article to be electroplated is removably positioned vertically to close the first open end and includes a thief laterally surrounding the article to define a cathode. An anode is positioned vertically to close the second open end, with the assembly defining a substantially closed, six-sided inner chamber for receiving an electrolyte therein for electroplating the article. The article and surrounding thief are coextensively aligned with the anode, with the floor, ceiling, front and back walls being effective for guiding electrical current flux between the cathode and the anode. In a preferred embodiment, the cell is disposed as an inner cell inside an outer cell substantially filled with the electrolyte, and a paddle is disposed inside the inner cell for agitating the electrolyte therein. The rack is removable and installable vertically upwardly which allows for automated handling thereof.

摘要翻译： 电镀电池包括形成具有第一和第二相对开口端的盒子的地板，天花板，前壁和后壁。 用于支撑待电镀的物品的支架可移除地垂直地定位以闭合第一开口端，并且包括围绕物品的小偷以限定阴极。 阳极被垂直定位以闭合第二开口端，其中组件限定了基本封闭的六面内腔，用于在其中容纳用于电镀物品的电解质。 物品和周围的小偷与阳极共同对准，地板，天花板，前壁和后壁对于引导阴极和阳极之间的电流通量是有效的。 在一个优选的实施方式中，将电池作为内部电池设置在基本上充满电解质的外部电池中，并且在内部电池内设置有用于搅拌电解质的电极。 机架是可拆卸的，可垂直向上安装，允许其自动处理。