公开(公告)号：US20080054393A1

公开(公告)日：2008-03-06

申请号：US11928798

申请日：2007-10-30

申请人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20070194390A1

公开(公告)日：2007-08-23

申请号：US11276282

申请日：2006-02-22

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/76

CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

摘要翻译： 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20070057343A1

公开(公告)日：2007-03-15

申请号：US11162471

申请日：2005-09-12

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L28/40

摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：US20070026659A1

公开(公告)日：2007-02-01

申请号：US11161217

申请日：2005-07-27

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/20

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

摘要翻译： 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

申请人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

发明人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US20070123015A1

公开(公告)日：2007-05-31

申请号：US11164634

申请日：2005-11-30

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Jeffrey Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony Stamper

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Jeffrey Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony Stamper

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

摘要翻译： 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US20070065966A1

公开(公告)日：2007-03-22

申请号：US11162661

申请日：2005-09-19

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L29/84

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US20070040239A1

公开(公告)日：2007-02-22

申请号：US11161832

申请日：2005-08-18

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Cotte ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Anthony Stamper ,  Eric White

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Cotte ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Anthony Stamper ,  Eric White

IPC分类号： H01L29/00

CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

公开(公告)号：US20070267698A1

公开(公告)日：2007-11-22

申请号：US11774853

申请日：2007-07-09

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Paul Kartschoke ,  Anthony Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Paul Kartschoke ,  Anthony Stamper

IPC分类号： H01L27/088 ,  H01L21/84

CPC分类号： H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

摘要翻译： 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。