利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

86 条记录 (耗时 0.026 秒)

    INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS
    2.
    发明申请
    INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS 有权
    金属栅极或硅化物上的MIM电容器与高K电介质材料的集成

    公开(公告)号：US20070057343A1

    公开(公告)日：2007-03-15

    申请号：US11162471

    申请日：2005-09-12

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/00

    CPC分类号： H01L28/40

    摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

    摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

    METHOD OF FABRICATING A PRECISION BURIED RESISTOR
    3.
    发明申请
    METHOD OF FABRICATING A PRECISION BURIED RESISTOR 有权
    制造精密电阻器的方法

    公开(公告)号：US20070194390A1

    公开(公告)日：2007-08-23

    申请号：US11276282

    申请日：2006-02-22

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/76

    CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

    摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

    摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
    5.
    发明申请
    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
    单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺

    公开(公告)号：US20070065966A1

    公开(公告)日：2007-03-22

    申请号：US11162661

    申请日：2005-09-19

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

    IPC分类号： H01L21/00 ,  H01L29/84

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    INTEGRATED BEOL THIN FILM RESISTOR
    6.
    发明申请
    INTEGRATED BEOL THIN FILM RESISTOR 有权
    集成波形薄膜电阻器

    公开(公告)号：US20070040239A1

    公开(公告)日：2007-02-22

    申请号：US11161832

    申请日：2005-08-18

    申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Cotte ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Anthony Stamper ,  Eric White

    发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Cotte ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Anthony Stamper ,  Eric White

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
    无平面化和相关半导体器件制造被动元件的方法

    公开(公告)号：US20080054393A1

    公开(公告)日：2008-03-06

    申请号：US11928798

    申请日：2007-10-30

    申请人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    发明人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    IPC分类号： H01L29/00 ,  H01L21/02

    CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

    摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    9.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 失效
    集成薄膜电阻与直接接触

    公开(公告)号：US20070166909A1

    公开(公告)日：2007-07-19

    申请号：US11275611

    申请日：2006-01-19

    申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/016

    摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。