公开(公告)号：US20080054393A1

公开(公告)日：2008-03-06

申请号：US11928798

申请日：2007-10-30

申请人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

申请人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

发明人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US20070241424A1

公开(公告)日：2007-10-18

申请号：US11279434

申请日：2006-04-12

申请人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L29/00

CPC分类号： H01G4/33 ,  H01G4/236 ,  H01L28/91 ,  Y10T29/435

摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.

摘要翻译： 电容器结构使用位于电介质层内的开口依次位于衬底上。 嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。 一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。 电容器介质层位于一对电容器板之间并填充孔。 可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。 或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

公开(公告)号：US20080047118A1

公开(公告)日：2008-02-28

申请号：US11924807

申请日：2007-10-26

申请人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Timothy Dalton ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01G7/00

CPC分类号： H01G4/33 ,  H01G4/236 ,  H01L28/91 ,  Y10T29/435

摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

摘要翻译： 电容器结构使用位于电介质层内的开口依次位于衬底上。 嵌入电介质层内的一对导体互连层终止于孔的一对相对的侧壁。 一对电容器板位于孔的一对相对的侧壁上，并接触一对导体互连层，但不填充孔。 电容器介质层位于一对电容器板之间并填充孔。 可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。 或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的侧壁是垂直的并且被向外倾斜的第二对相对的侧壁隔开时。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20070267698A1

公开(公告)日：2007-11-22

申请号：US11774853

申请日：2007-07-09

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Paul Kartschoke ,  Anthony Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Paul Kartschoke ,  Anthony Stamper

IPC分类号： H01L27/088 ,  H01L21/84

CPC分类号： H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

摘要翻译： 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：US20050218504A1

公开(公告)日：2005-10-06

申请号：US10708883

申请日：2004-03-30

申请人： Timothy Dalton ,  John Fitzsimmons ,  Anthony Stamper

发明人： Timothy Dalton ,  John Fitzsimmons ,  Anthony Stamper

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/14 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/31695 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an embodiment of the invention, a dielectric material comprises a matrix of a material selected from the group consisting essentially of organic materials, inorganic materials and organo-silicate materials; a plurality of pores dispersed throughout the matrix; and a gas filling the pores. The gas is selected from the group consisting essentially of inert gases, depositing gases, and breakdown suppressing gases. The filled pore dielectric material is suitably used in a damascene wiring layer. In further embodiments, a plasma device comprises an integrated circuit (IC) chip substrate; at least one dielectric layer having a thickness on a surface of the substrate, a cavity formed in the dielectric layer, at least two electrodes disposed in the cavity; and a plasma gas filling the cavity. The plasma device can operate as a light source or as a switch.

摘要翻译： 在本发明的一个实施方案中，电介质材料包括选自基本上由有机材料，无机材料和有机硅酸盐材料组成的组的基体; 分散在整个基质中的多个孔; 和填充孔的气体。 气体选自基本上由惰性气体，沉积气体和击穿抑制气体组成的组。 填充孔介电材料适用于镶嵌布线层。 在另外的实施例中，等离子体器件包括集成电路（IC）芯片衬底; 至少一个介电层，其具有在所述基板的表面上的厚度，在所述介电层中形成的空腔，设置在所述空腔中的至少两个电极; 以及填充空腔的等离子体气体。 等离子体装置可以作为光源或开关操作。

公开(公告)号：US20070132067A1

公开(公告)日：2007-06-14

申请号：US11557668

申请日：2006-11-08

申请人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

发明人： Timothy Dalton ,  Jeffrey Gambino ,  Mark Jaffe ,  Stephen Luce ,  Edmund Sprogis

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

摘要翻译： 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。 第一个方向基本上平行于共同的表面。

公开(公告)号：US09059000B2

公开(公告)日：2015-06-16

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/11

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。