公开(公告)号：US20080054393A1

公开(公告)日：2008-03-06

申请号：US11928798

申请日：2007-10-30

申请人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20070194390A1

公开(公告)日：2007-08-23

申请号：US11276282

申请日：2006-02-22

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/76

CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

公开(公告)号：US20070152332A1

公开(公告)日：2007-07-05

申请号：US11306596

申请日：2006-01-04

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Vincent McGahay ,  Anthony Stamper ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.

摘要翻译： 本发明涉及包括通孔级布线和/或器件的集成电路。 具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。 第一和第二线路级均包括金属布线和/或电子设备。 通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。 此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

公开(公告)号：US20070057343A1

公开(公告)日：2007-03-15

申请号：US11162471

申请日：2005-09-12

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L28/40

摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：US20070026659A1

公开(公告)日：2007-02-01

申请号：US11161217

申请日：2005-07-27

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/20

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

摘要翻译： 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US20080185684A1

公开(公告)日：2008-08-07

申请号：US12098479

申请日：2008-04-07

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

公开(公告)号：US20060270247A1

公开(公告)日：2006-11-30

申请号：US10908789

申请日：2005-05-26

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

IPC分类号： H01L21/336

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28194 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

摘要： Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

摘要翻译： 公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及 臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。 在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。 本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

公开(公告)号：US07439151B2

公开(公告)日：2008-10-21

申请号：US11531298

申请日：2006-09-13

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

摘要翻译： 一种用于在双镶嵌加工中整合金属 - 绝缘体 - 金属（MIM）电容器的形成的方法包括在其中形成具有较低电容器电极和一个或多个下部金属线的较低层间电介质（ILD）层，所述ILD层具有第一 在其上形成介电覆盖层。 上ILD层形成在下ILD层上，并且通孔和上线结构限定在上ILD层内。 通孔和上线结构填充有平坦化层，然后在平坦化层上形成和图案化抗蚀剂层。 上部电容器电极结构限定在对应于抗蚀剂的去除部分的上部ILD层中。 通孔，上线结构和上电容器电极结构填充有导电材料，其中MIM电容器由下电容器电极，第一介电覆盖层和上电容器电极结构限定。

公开(公告)号：US20080064163A1

公开(公告)日：2008-03-13

申请号：US11531298

申请日：2006-09-13

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/8242

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

摘要翻译： 一种用于在双镶嵌加工中整合金属 - 绝缘体 - 金属（MIM）电容器的形成的方法包括在其中形成具有较低电容器电极和一个或多个下部金属线的较低层间电介质（ILD）层，所述ILD层具有第一 在其上形成介电覆盖层。 上ILD层形成在下ILD层上，并且通孔和上线结构限定在上ILD层内。 通孔和上线结构填充有平坦化层，然后在平坦化层上形成和图案化抗蚀剂层。 上部电容器电极结构限定在对应于抗蚀剂的去除部分的上部ILD层中。 通孔，上线结构和上电容器电极结构填充有导电材料，其中MIM电容器由下电容器电极，第一介电覆盖层和上电容器电极结构限定。

公开(公告)号：US20060197119A1

公开(公告)日：2006-09-07

申请号：US11164765

申请日：2005-12-05

申请人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L29/80

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。