公开(公告)号：US20190229128A1

公开(公告)日：2019-07-25

申请号：US16267151

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Bok Hoen KIM ,  Sang Hyuk KIM ,  Myung Hun JU ,  Hyung Jin PARK ,  Ryeun Kwan KIM ,  Jin Chul SON ,  Saiprasanna GNANAVELU ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Majid K. SHAHREZA ,  Jason K. FOSTER

IPC: H01L27/11582 ,  C23C16/455 ,  C23C16/40 ,  H01L29/06 ,  C23C16/505 ,  C23C16/52 ,  C23C16/02 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/768

CPC classification number: H01L27/11582 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45523 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/76801 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/06

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

公开(公告)号：US20170062469A1

公开(公告)日：2017-03-02

申请号：US15214104

申请日：2016-07-19

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Bok Hoen KIM ,  Sang Hyuk KIM ,  Myung Hun JU ,  Hyung Jin PARK ,  Ryeun Kwan KIM ,  Jin Chul SON ,  Saiprasanna GNANAVELU ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Majid K. SHAHREZA ,  Jason K. FOSTER

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/324

CPC classification number: H01L27/11582 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45523 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/76801 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/06

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract translation: 本公开的实施例通常涉及用于形成用于3D NAND结构中的层间电介质（ILD）层的电介质膜叠层的改进方法。 在一个实施例中，该方法包括提供其上沉积有栅极叠层的衬底，其中使用第一RF功率在栅极堆叠的暴露表面上形成第一氧化物层，以及第一工艺气体，其包括TEOS气体和第一含氧气体 并且使用第二RF功率在第一氧化物层上形成第二氧化物层，以及包括硅烷气体和第二含氧气体的第二工艺气体。

公开(公告)号：US20160049323A1

公开(公告)日：2016-02-18

申请号：US14824229

申请日：2015-08-12

Applicant: Applied Materials, Inc.

Inventor： Zheng John YE ,  Jay D. PINSON, II ,  Hiroji HANAWA ,  Jianhua ZHOU ,  Xing LIN ,  Ren-Guan DUAN ,  Kwangduk Douglas LEE ,  Bok Hoen KIM ,  Swayambhu P. BEHERA ,  Sungwon HA ,  Ganesh BALASUBRAMANIAN ,  Juan Carlos ROCHA- ALVAREZ ,  Prashant Kumar KULSHRESHTHA ,  Jason K. FOSTER ,  Mukund SRINIVASAN ,  Uwe P. HALLER ,  Hari K. PONNEKANTI

IPC: H01L21/683 ,  H02N13/00

CPC classification number: H01L21/6833 ,  H01L21/68757 ,  H02N13/00

Abstract: Embodiments of the present disclosure provide an electrostatic chuck for maintaining a flatness of a substrate being processed in a plasma reactor at high temperatures. In one embodiment, the electrostatic chuck comprises a chuck body coupled to a support stem, the chuck body having a substrate supporting surface, and the chuck body has a volume resistivity value of about 1×107 ohm-cm to about 1×1015 ohm-cm in a temperature of about 250° C. to about 700° C., and an electrode embedded in the body, the electrode is coupled to a power supply. In one example, the chuck body is composed of an aluminum nitride material which has been observed to be able to optimize chucking performance around 600° C. or above during a deposition or etch process, or any other process that employ both high operating temperature and substrate clamping features.

Abstract translation: 本公开的实施例提供了一种静电卡盘，用于在高温下维持在等离子体反应器中正在加工的基板的平坦度。 在一个实施例中，静电卡盘包括联接到支撑杆的卡盘体，卡盘主体具有基底支撑表面，卡盘体的体积电阻率值约为1×107ohm-cm至约1×1015ohm- 在约250℃至约700℃的温度下，以及嵌入在本体中的电极，电极耦合到电源。 在一个实例中，卡盘主体由氮化铝材料组成，已经被观察到能够在沉积或蚀刻过程期间优化约600℃或更高的夹持性能，或任何其他使用高工作温度和 基板夹紧功能。

公开(公告)号：US20140261703A1

公开(公告)日：2014-09-18

申请号：US14188629

申请日：2014-02-24

Applicant: Applied Materials, Inc.

Inventor： Daemian RAJ ,  Juan Carlos ROCHA-ALVAREZ ,  Jason K. FOSTER ,  Bo XIE ,  Alexandros T. DEMOS

IPC: F16K37/00

CPC classification number: F16K37/0091 ,  Y10T137/0318 ,  Y10T137/8326

Abstract: Methods for detecting valve leakage and apparatus for the same are provided. In one embodiment, a method for detecting a valve leakage includes flowing a gas through a diverter valve, determining a pressure in a gas source provided to the diverter valve, comparing the determined pressure value with an expected pressure value, and generating a signal in response to the comparison.

Abstract translation: 提供了检测阀门泄漏的方法及其设备。 在一个实施例中，一种用于检测阀泄漏的方法包括使气体流过分流阀，确定提供给转向阀的气源中的压力，将所确定的压力值与预期压力值进行比较，并产生响应的信号 比较。