公开(公告)号：US20190229128A1

公开(公告)日：2019-07-25

申请号：US16267151

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Bok Hoen KIM ,  Sang Hyuk KIM ,  Myung Hun JU ,  Hyung Jin PARK ,  Ryeun Kwan KIM ,  Jin Chul SON ,  Saiprasanna GNANAVELU ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Majid K. SHAHREZA ,  Jason K. FOSTER

IPC: H01L27/11582 ,  C23C16/455 ,  C23C16/40 ,  H01L29/06 ,  C23C16/505 ,  C23C16/52 ,  C23C16/02 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/768

CPC classification number: H01L27/11582 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45523 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/76801 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/06

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

公开(公告)号：US20190122872A1

公开(公告)日：2019-04-25

申请号：US16230766

申请日：2018-12-21

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Sanjeev BALUJA ,  Mayur G. KULKARNI ,  Shailendra SRIVASTAVA ,  Tejas ULAVI ,  Yusheng ALVIN ZHOU ,  Amit Kumar BANSAL ,  Priyanka DASH ,  Zhijun JIANG ,  Ganesh BALASUBRAMANIAN ,  Qiang MA ,  Kaushik ALAYAVALLI ,  Yuxing ZHANG ,  Daniel HWUNG ,  Shawyon JAFARI

IPC: H01J37/32 ,  C23C16/52 ,  C23C16/455

Abstract: Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.

公开(公告)号：US20160181088A1

公开(公告)日：2016-06-23

申请号：US14975133

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Kien N. CHUC ,  Sungjin KIM ,  Yanjie WANG

IPC: H01L21/02

CPC classification number: C23C16/4412 ,  C23C16/4401 ,  H01J37/32477

Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

Abstract translation: 本文公开了一种用于处理衬底的处理室。 在一个实施例中，处理室包括设置在处理室的内部容积内的衬套组件，以及设置在室的内部容积中的C形通道，其限定衬套组件。 在另一个实施例中，本文公开了一种设置在处理室的内部容积中的处理套件。 该处理套件包括衬套组件，C通道和设置在内部容积中的隔离器。 C通道和隔离器限定衬套组件。 本文还描述了通过将前体气体流入处理室中将硅基材料沉积在基底上的方法。

公开(公告)号：US20200058538A1

公开(公告)日：2020-02-20

申请号：US16664396

申请日：2019-10-25

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Praket P. JHA ,  Krishna NITTALA

IPC: H01L21/687 ,  C23C16/458

Abstract: Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin.

公开(公告)号：US20170062469A1

公开(公告)日：2017-03-02

申请号：US15214104

申请日：2016-07-19

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung TSIANG ,  Praket P. JHA ,  Xinhai HAN ,  Bok Hoen KIM ,  Sang Hyuk KIM ,  Myung Hun JU ,  Hyung Jin PARK ,  Ryeun Kwan KIM ,  Jin Chul SON ,  Saiprasanna GNANAVELU ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Majid K. SHAHREZA ,  Jason K. FOSTER

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/324

CPC classification number: H01L27/11582 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45523 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/76801 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/06

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract translation: 本公开的实施例通常涉及用于形成用于3D NAND结构中的层间电介质（ILD）层的电介质膜叠层的改进方法。 在一个实施例中，该方法包括提供其上沉积有栅极叠层的衬底，其中使用第一RF功率在栅极堆叠的暴露表面上形成第一氧化物层，以及第一工艺气体，其包括TEOS气体和第一含氧气体 并且使用第二RF功率在第一氧化物层上形成第二氧化物层，以及包括硅烷气体和第二含氧气体的第二工艺气体。

公开(公告)号：US20190311887A1

公开(公告)日：2019-10-10

申请号：US16369911

申请日：2019-03-29

Applicant: Applied Materials, Inc.

Inventor： Akshay GUNAJI ,  Tuan Anh NGUYEN ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Kurt LANGELAND

IPC: H01J37/32 ,  C23C16/455

Abstract: The present disclosure relates to a fluid delivery system assembly for use with a semiconductor process chamber. A series of three-way valves control process fluid flow between process fluid conduits which lead to the process chamber and a divert conduit.

公开(公告)号：US20180274095A1

公开(公告)日：2018-09-27

申请号：US15992330

申请日：2018-05-30

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Kien N. CHUC ,  Sungjin KIM ,  Yanjie WANG

IPC: C23C16/44 ,  H01J37/32

Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

公开(公告)号：US20170125280A1

公开(公告)日：2017-05-04

申请号：US15333345

申请日：2016-10-25

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Praket P. JHA ,  Krishna NITTALA

IPC: H01L21/687 ,  C23C16/458 ,  C23C16/52 ,  H01L21/683

CPC classification number: H01L21/68742 ,  C23C16/4581 ,  H01L21/68757

Abstract: Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin.

公开(公告)号：US20200325577A1

公开(公告)日：2020-10-15

申请号：US16912417

申请日：2020-06-25

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Mayur G. KULKARNI ,  Sanjeev BALUJA ,  Kien N. CHUC ,  Sungjin KIM ,  Yanjie WANG

IPC: C23C16/44 ,  H01J37/32

Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

公开(公告)号：US20180261453A1

公开(公告)日：2018-09-13

申请号：US15917079

申请日：2018-03-09

Applicant: Applied Materials, Inc.

Inventor： Kalyanjit GHOSH ,  Sanjeev BALUJA ,  Mayur G. KULKARNI

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/44 ,  C23C16/455

CPC classification number: H01L21/02274 ,  C23C16/4408 ,  C23C16/45502 ,  H01J37/3244 ,  H01J37/32862 ,  H01L21/02208

Abstract: Apparatus and methods for depositing a film in a PECVD chamber while simultaneously flowing a purge gas from beneath a substrate support are provided herein. In embodiments disclosed herein, a combined gas exhaust volume circumferentially disposed about the substrate support, below a first volume and above a second volume, draws processing gases from the first volume down over an edge of a first surface of the substrate support and simultaneously draws purge gases from the second volume upward over an edge of a second surface of the substrate support. The gases are than evacuated from the combined exhaust volume through an exhaust port fluidly coupled to a vacuum source.