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    Intrench profile
    2.
    发明授权
    Intrench profile 有权

    公开(公告)号：US09012302B2

    公开(公告)日：2015-04-21

    申请号：US14484152

    申请日：2014-09-11

    Applicant: Applied Materials, Inc.

    Inventor： Kedar Sapre ,  Nitin Ingle ,  Jing Tang

    IPC: H01L21/76 ,  H01L21/3065 ,  H01L21/308

    CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

    INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION
    3.
    发明申请
    INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION 审中-公开
    用于半导体集成的敏感干燥除去过程

    公开(公告)号：US20130260564A1

    公开(公告)日：2013-10-03

    申请号：US13624693

    申请日：2012-09-21

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Kedar Sapre ,  Rossella Mininni ,  Jing Tang

    IPC: H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/31116 ,  H01L29/66545

    Abstract: Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF.

    Abstract translation: 公开了从半导体衬底的表面沉积和蚀刻电介质层的方法。 所述方法可以包括在HF水溶液中沉积具有第一湿蚀刻速率的第一介电层。 所述方法还可以包括沉积第二电介质层，其可以在沉积之后最初可流动，并且第二介电层可以具有高于第一湿蚀刻速率的HF水溶液中的第二湿蚀刻速率。 所述方法可以进一步包括用蚀刻剂气体混合物蚀刻第一和第二介电层，其中第一和第二介电层具有比第二湿蚀刻速率与第一湿蚀刻的比率更接近的蚀刻速率比 在HF水溶液中。

    INTRENCH PROFILE
    4.
    发明申请
    INTRENCH PROFILE 有权
    INTRENCH简档

    公开(公告)号：US20150031211A1

    公开(公告)日：2015-01-29

    申请号：US14484152

    申请日：2014-09-11

    Applicant: Applied Materials, Inc.

    Inventor： Kedar Sapre ,  Nitin Ingle ,  Jing Tang

    IPC: H01L21/3065 ,  H01L21/308

    CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

    Abstract translation: 描述了蚀刻半导体衬底中的凹部的方法。 该方法可以包括在衬底的沟槽中形成介质衬垫层，其中衬层具有第一密度。 该方法还可以包括至少部分地在衬垫层上的沟槽中沉积第二电介质层。 第二电介质层可以首先在沉积之后流动，并且具有小于衬垫的第一密度的第二密度。 该方法可以进一步包括将衬底暴露于干燥蚀刻剂，其中蚀刻剂去除第一衬里层和第二介电层的一部分以形成凹部，其中干蚀刻剂包括含氟化合物和分子氢，并且其中 用于去除第一介电衬垫层以去除第二介电层的蚀刻速率比为约1:1.2至约1:1。

    Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof
    5.
    发明授权
    Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof 有权
    适用于窄间距应用的半导体器件及其制造方法

    公开(公告)号：US09530898B2

    公开(公告)日：2016-12-27

    申请号：US14515767

    申请日：2014-10-16

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Udayan Ganguly ,  Yoshitaka Yokota ,  Jing Tang ,  Sunderraj Thirupapuliyur ,  Christopher Sean Olsen ,  Shiyu Sun ,  Tze Wing Poon ,  Wei Liu ,  Johanes Swenberg ,  Vicky U. Nguyen ,  Swaminathar Srinivasan ,  Jacob Newman

    IPC: H01L29/788 ,  H01L21/67 ,  H01L21/762 ,  H01L27/115

    CPC classification number: H01L29/788 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76232 ,  H01L27/11521

    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

    Abstract translation: 适用于窄间距应用的半导体器件及其制造方法在本文中描述。 在一些实施例中，半导体器件可以包括具有接近浮动栅极的基极的第一宽度的浮动栅极，该第一宽度大于靠近浮动栅极顶部的第二宽度。 在一些实施例中，成形材料层的方法可以包括（a）氧化材料层的表面以以初始速率形成氧化物层; （b）当氧化速率为初始速率的约90％或更低时终止氧化物层的形成; （c）通过蚀刻工艺去除至少一些氧化物层; 和（d）重复（a）到（c）直到材料层形成所需的形状。 在一些实施例中，材料层可以是半导体器件的浮置栅极。

    Intrench profile
    7.
    发明授权
    Intrench profile 有权
    精心设计

    公开(公告)号：US08927390B2

    公开(公告)日：2015-01-06

    申请号：US13624724

    申请日：2012-09-21

    Applicant: Applied Materials, Inc.

    Inventor： Kedar Sapre ,  Nitin Ingle ,  Jing Tang

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

    Abstract translation: 描述了蚀刻半导体衬底中的凹部的方法。 该方法可以包括在衬底的沟槽中形成介质衬垫层，其中衬层具有第一密度。 该方法还可以包括至少部分地在衬垫层上的沟槽中沉积第二电介质层。 第二电介质层可以首先在沉积之后流动，并且具有小于衬垫的第一密度的第二密度。 该方法可以进一步包括将衬底暴露于干燥蚀刻剂，其中蚀刻剂去除第一衬里层和第二介电层的一部分以形成凹部，其中干蚀刻剂包括含氟化合物和分子氢，并且其中 用于去除第一介电衬垫层以去除第二介电层的蚀刻速率比为约1:1.2至约1:1。

    INTRENCH PROFILE
    8.
    发明申请
    INTRENCH PROFILE 有权

    公开(公告)号：US20130260533A1

    公开(公告)日：2013-10-03

    申请号：US13624724

    申请日：2012-09-21

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Kedar Sapre ,  Nitin Ingle ,  Jing Tang

    IPC: H01L21/762

    CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

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