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23 条记录 (耗时 0.016 秒)

    CVD BASED SPACER DEPOSITION WITH ZERO LOADING
    1.
    发明申请
    CVD BASED SPACER DEPOSITION WITH ZERO LOADING 审中-公开

    公开(公告)号：US20200043722A1

    公开(公告)日：2020-02-06

    申请号：US16514534

    申请日：2019-07-17

    申请人： Applied Materials, Inc.

    发明人： Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar N. KEDLAYA

    IPC分类号： H01L21/02 ,  H01L21/033

    摘要： Embodiments of the present disclosure relate to deposition methods for dielectric layers with zero pattern loading characteristics. In one embodiment, the method includes depositing a conformal dielectric layer on the substrate having a patterned area and a blanket area by exposing the substrate to a deposition precursor and a tuning gas simultaneously without the presence of plasma in a process chamber, wherein the deposition precursor is reacted to form a chemical reaction by-product, and the chemical reaction by-product is the same as the tuning gas, and wherein the deposition precursor and the tuning gas are provided at an amount that is more than required for the deposition reaction to occur at the patterned area and the blanket area.

    SHADOW RING LIFT TO IMPROVE WAFER EDGE PERFORMANCE
    5.
    发明申请
    SHADOW RING LIFT TO IMPROVE WAFER EDGE PERFORMANCE 有权

    公开(公告)号：US20230002894A1

    公开(公告)日：2023-01-05

    申请号：US17473118

    申请日：2021-09-13

    申请人： Applied Materials, Inc.

    发明人： Zubin HUANG ,  Jallepally Ravi ,  Kai WU ,  Xiaoxiong YUAN

    IPC分类号： C23C16/458 ,  H01J37/32 ,  H01L21/687 ,  H01L21/768 ,  H01L23/532 ,  C23C16/50 ,  C23C16/06

    摘要： A method and apparatus for processing a substrate are described herein. The methods and apparatus described enable the raising and lowering of a shadow ring within a process chamber either simultaneously with or separately from a plurality of substrate lift pins. The shadow ring is raised and lowered using a shadow ring lift assembly and may be raised to a pre-determined height above the substrate during a radical treatment operation. The shadow ring lift assembly may also raise and lower the plurality of substrate lift pins to enable both the shadow ring and the substrate lift pins to be raised to a transfer position when the substrate is being transferred into or out of the process chamber.

    REMOTE CAPACITIVELY COUPLED PLASMA DEPOSITION OF AMORPHOUS SILICON
    6.
    发明申请
    REMOTE CAPACITIVELY COUPLED PLASMA DEPOSITION OF AMORPHOUS SILICON 有权

    公开(公告)号：US20210040617A1

    公开(公告)日：2021-02-11

    申请号：US16980325

    申请日：2019-03-13

    申请人： Applied Materials, Inc.

    发明人： Zubin HUANG ,  Rui CHENG ,  Chen-An CHEN ,  Karthik JANAKIRAMAN

    IPC分类号： C23C16/50 ,  C23C16/24 ,  C23C16/455

    摘要： Method for depositing amorphous silicon materials are provide and include generating a plasma within a plasma unit in fluid communication with a process chamber and flowing the plasma through an ion suppressor to produce an activated fluid containing reactive species and neutral species. The activated fluid either contains no ions or contains a lower concentration of ions than the plasma. The method further includes flowing the activated fluid into a first inlet of a dual channel showerhead within the process chamber and flowing a silicon precursor into a second inlet of the dual channel showerhead. Thereafter, the method includes flowing a mixture of the activated fluid and the silicon precursor out of the dual channel showerhead and forming an amorphous silicon layer on a substrate disposed in the process chamber.

    MULTIPLE SPACER PATTERNING SCHEMES
    10.
    发明申请
    MULTIPLE SPACER PATTERNING SCHEMES 审中-公开

    公开(公告)号：US20200335338A1

    公开(公告)日：2020-10-22

    申请号：US16821759

    申请日：2020-03-17

    申请人： Applied Materials, Inc.

    发明人： Tzu-Shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KADLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

    IPC分类号： H01L21/033

    摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.