ADC with capacitive difference circuit and digital sigma-delta feedback

    公开(公告)号:US10135459B2

    公开(公告)日:2018-11-20

    申请号:US15334011

    申请日:2016-10-25

    IPC分类号: H03M3/00 A61B5/0428 A61B5/00

    摘要: A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference.

    ELECTRICAL NETWORKS AND METHODS OF FORMING THE SAME
    2.
    发明申请
    ELECTRICAL NETWORKS AND METHODS OF FORMING THE SAME 有权
    电气网络及其形成方法

    公开(公告)号:US20120130654A1

    公开(公告)日:2012-05-24

    申请号:US13298210

    申请日:2011-11-16

    CPC分类号: H03K17/56 H03H7/40 H03H11/28

    摘要: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

    摘要翻译: 基于认识到制造变化引入旨在相同的电子子网络的轻微差异,形成电网络以产生至少一个期望的性能特征的近似。 通过提供一个子网络池,然后选择性地连接这些子网络的特定组合来实现近似所期望的性能特征的网络,这些制造差异变得有利。 子网络类似(例如,电阻器)并且具有相似的测量。

    Amplifier circuit with reduced DC power related transients
    3.
    发明授权
    Amplifier circuit with reduced DC power related transients 失效
    降低直流功率相关瞬变的放大器电路

    公开(公告)号:US5703529A

    公开(公告)日:1997-12-30

    申请号:US609726

    申请日:1996-03-01

    IPC分类号: H03F1/26 H03F1/30 H03F3/30

    CPC分类号: H03F1/305 H03F3/3081 H03F3/72

    摘要: An amplifier circuit with improved turn-on transient operation includes a differential amplifier and a selectively variable reference generator for controlling the amplifier output during circuit turn-on. The amplifier is biased by a single power supply and its differential inputs are driven by a reference voltage from the reference generator and a single-ended input signal. Following circuit turn-on, the selectively variable reference voltage, generated by charging the bypass capacitor with a constant current source, charges in a linear manner from ground potential toward its final value of, typically, half of the power supply voltage. This allows improved turn-on transient operation to be realized, e.g. reduced "pops" and "clicks" upon circuit turn-on, while giving the user increased flexibility in selecting the sizes of the reference voltage bypass capacitor and the input signal coupling capacitor.

    摘要翻译: 具有改善的导通瞬态操作的放大器电路包括差分放大器和用于在电路接通期间控制放大器输出的选择性可变参考发生器。 放大器由单个电源偏置,其差分输入由参考发生器的参考电压和单端输入信号驱动。 继电路导通后,通过用恒定电流源对旁路电容器充电而产生的选择性可变参考电压以线性方式从地电位向其最终值(通常为电源电压的一半)充电。 这允许实现改进的导通瞬态操作,例如, 在电路开启时减少“流行”和“点击”,同时为用户提供了选择参考电压旁路电容器和输入信号耦合电容器尺寸的灵活性。

    Apparatus and methods for forming electrical networks that approximate desired performance characteristics
    5.
    发明授权
    Apparatus and methods for forming electrical networks that approximate desired performance characteristics 有权
    用于形成近似所需性能特征的电网的装置和方法

    公开(公告)号:US08502557B2

    公开(公告)日:2013-08-06

    申请号:US11810517

    申请日:2007-06-05

    IPC分类号: H03K17/16 H03K19/003

    CPC分类号: H03K17/56 H03H7/40 H03H11/28

    摘要: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

    摘要翻译: 基于认识到制造变化引入旨在相同的电子子网络的轻微差异,形成电网络以产生至少一个期望的性能特征的近似。 通过提供一个子网络池,然后选择性地连接这些子网络的特定组合来实现近似所期望的性能特征的网络,这些制造差异变得有利。 子网络类似(例如,电阻器)并且具有相似的测量。

    Electrical networks and methods of forming the same
    7.
    发明授权
    Electrical networks and methods of forming the same 有权
    电网及其形成方法

    公开(公告)号:US08598904B2

    公开(公告)日:2013-12-03

    申请号:US13298210

    申请日:2011-11-16

    IPC分类号: H03K17/16 H03K19/003

    CPC分类号: H03K17/56 H03H7/40 H03H11/28

    摘要: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

    摘要翻译: 基于认识到制造变化引入旨在相同的电子子网络的轻微差异,形成电网络以产生至少一个期望的性能特征的近似。 通过提供一个子网络池,然后选择性地连接这些子网络的特定组合来实现近似所期望的性能特征的网络,这些制造差异变得有利。 子网络类似(例如,电阻器)并且具有相似的测量。

    Buffer circuit for op amp output stage
    8.
    发明授权
    Buffer circuit for op amp output stage 有权
    运放输出级缓冲电路

    公开(公告)号:US06714076B1

    公开(公告)日:2004-03-30

    申请号:US10272172

    申请日:2002-10-15

    申请人: Arthur J. Kalb

    发明人: Arthur J. Kalb

    IPC分类号: H03F345

    摘要: An op amp includes a pair of buffer amplifiers interposed between the current switch and the output transistors in an output stage based on the Monticelli architecture. The buffer amps buffer the output transistors' gate capacitances, thereby allowing the output transistors to be nearly any desired size without adversely affecting the op amp's dynamic performance. This enables the op amp's compensation capacitors to set the amplifier's bandwidth, and allows the secondary pole to be at a higher frequency. The buffer amplifiers can also provide gain which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. In addition, the buffer amplifiers can be used to provide voltage level translation between the current switch and output transistors, which can provide additional headroom for the op amp's gain stage.

    摘要翻译: 运算放大器包括基于Monticelli架构的输入级中插入在电流开关和输出晶体管之间的一对缓冲放大器。 缓冲放大器缓冲输出晶体管的栅极电容,从而允许输出晶体管几乎达到所需的大小,而不会对运算放大器的动态性能产生不利影响。 这使得运算放大器的补偿电容器可以设置放大器的带宽,并允许辅助极点处于更高的频率。 缓冲放大器还可以提供增益,其有效地乘以输出晶体管的跨导,并进一步延伸到次级极点位置。 此外,缓冲放大器可用于在电流开关和输出晶体管之间提供电压电平转换,这可为运算放大器的增益级提供额外的余量。

    Differential stage voltage offset trim circuitry
    9.
    发明授权
    Differential stage voltage offset trim circuitry 有权
    差分电压补偿电路

    公开(公告)号:US07049889B2

    公开(公告)日:2006-05-23

    申请号:US10911371

    申请日:2004-08-03

    申请人: Arthur J. Kalb

    发明人: Arthur J. Kalb

    IPC分类号: H03F3/45

    摘要: Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (Vos) error for a “main” differential pair. One trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim Vos error due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim Vos error that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.

    摘要翻译: 差分级电压偏移调整电路涉及使用一个或多个微调电路,每个微调电路专用于修整“主”差分对的一个特定电压偏移源(V OUT)。 一个微调电路可以专用于修剪由于主对阈值电压之间的失配而产生的错误,并且另一个微调电路可以专用于修整V OSOS错误 这是由于主要对的β值之间的不匹配引起的。 另一个微调电路可以由于主对晶体管之间的伽马不匹配而修正V OS错误,并且可以采用相应的微调电路来修正由于阈值失配引起的V OSO错误 和/或由主对驱动的有源负载的晶体管之间的β失配。 可以同时采用多个微调电路来减少由多个源中的每一个产生的偏移误差。

    Accurate charge-dividing digital-to-analog converter
    10.
    发明授权
    Accurate charge-dividing digital-to-analog converter 失效
    精确的分频数模转换器

    公开(公告)号:US5923275A

    公开(公告)日:1999-07-13

    申请号:US955904

    申请日:1997-10-22

    申请人: Arthur J. Kalb

    发明人: Arthur J. Kalb

    CPC分类号: H03M1/68 H03M1/1028 H03M1/806

    摘要: A structure and a method are provided to convert the value of a digital word to an analog signal representing that value, using a small and simple charge divide-by-four circuit with one op amp. The D/A converter thus provided greatly reduces the effects of capacitor mismatch. The D/A converter processes one bit pair at a time and stores a corresponding charge. This charge is divided by four prior to processing the next bit pair. In one embodiment, the D/A converter has one operational amplifier, two capacitors, and seven switches. In another embodiment, the same number of elements are used in a different configuration, which allows an offset correction to be performed. In yet another embodiment, the D/A converter has one op amp, four capacitors, and eleven switches, which allows both offset voltage and gain compensation correction.

    摘要翻译: 提供一种结构和方法,使用具有一个运算放大器的小且简单的电荷分频电路将数字字的值转换为表示该值的模拟信号。 这样提供的D / A转换器大大降低了电容器失配的影响。 D / A转换器一次处理一个位对并存储相应的电荷。 在处理下一个位对之前,该电荷除以四。 在一个实施例中,D / A转换器具有一个运算放大器,两个电容器和七个开关。 在另一个实施例中,在不同的配置中使用相同数量的元件,这允许执行偏移校正。 在另一个实施例中,D / A转换器具有一个运算放大器,四个电容器和十一个开关,其允许偏移电压和增益补偿校正。