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    Automating photolithography in the fabrication of integrated circuits
    2.
    发明授权
    Automating photolithography in the fabrication of integrated circuits 失效
    在制造集成电路时自动化光刻

    公开(公告)号：US5663076A

    公开(公告)日：1997-09-02

    申请号：US512678

    申请日：1995-08-08

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Automating photolithography in the fabrication of integrated circuits
    4.
    发明授权
    Automating photolithography in the fabrication of integrated circuits 失效
    在制造集成电路时自动化光刻

    公开(公告)号：US06418353B1

    公开(公告)日：2002-07-09

    申请号：US09064802

    申请日：1998-04-22

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G06F1900

    CPC分类号： G03F7/705 ,  G03F7/70433 ,  G03F7/70625

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 制造数据包括流程和。 然后将产量参数转移回瑞利处理器用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Automating photolithography in the fabrication of integrated circuits
    6.
    再颁专利
    Automating photolithography in the fabrication of integrated circuits 有权
    在制造集成电路时自动化光刻

    公开(公告)号：USRE38900E1

    公开(公告)日：2005-11-29

    申请号：US09273171

    申请日：1999-03-19

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Process for forming low dielectric constant insulation layer on integrated circuit structure
    7.
    发明授权
    Process for forming low dielectric constant insulation layer on integrated circuit structure 失效
    在集成电路结构上形成低介电常数绝缘层的工艺

    公开(公告)号：US5393712A

    公开(公告)日：1995-02-28

    申请号：US84829

    申请日：1993-06-28

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L21/02304 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02343 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76829 ,  H01L2221/1047

    摘要： A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material. The second liquid is then preferably removed from the matrix-forming material either by lyophilizing (freeze drying) or by raising the pressure and temperature above the critical point of the second liquid.

    摘要翻译： 描述了一种用于在半导体晶片上的集成电路结构上形成低介电常数绝缘层的工艺，首先在集成电路结构上形成复合层，该复合层包括一种或多种可提取材料和一种或多种矩阵形成绝缘材料 半导体晶片，然后从基质形成材料中选择性地除去可提取材料，而不损坏剩余的基体材料，从而留下绝缘材料的多孔基体。 在一个实施方案中，复合层由凝胶形成。 通过首先将其溶解在不是基质形成材料的溶剂形成溶液的第一液体中来除去可萃取材料。 然后通过在与第一溶剂混溶的第二液体中冲洗基质并且也不是基质形成材料的溶剂，从基质形成材料中除去该溶液。 然后优选通过冻干（冷冻干燥）或通过将压力和温度升高到高于第二液体的临界点的方式从基质形成材料中除去第二液体。

    Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
    8.
    发明授权
    Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys 失效
    在硅和硅合金中使用互补结场效应晶体管和MOS晶体管的集成电路

    公开(公告)号：US07569873B2

    公开(公告)日：2009-08-04

    申请号：US11261873

    申请日：2005-10-28

    申请人： Ashok K. Kapoor

    发明人： Ashok K. Kapoor

    IPC分类号： H01L29/80 ,  H01L21/70

    CPC分类号： H01L29/808 ,  H01L21/2257 ,  H01L27/0611 ,  H01L27/098 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66901 ,  H01L29/7833

    摘要： This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

    摘要翻译： 本发明描述了使用硅中的结型场效应晶体管构建互补逻辑电路的方法。 本发明理想地适用于深亚微米尺寸，优选低于65nm。 本发明的基础是在增强模式下操作的互补结型场效应晶体管。 JFET的速度功率性能可以与次级70纳米尺寸的CMOS器件相媲美。 然而，JFET的最大电源电压仍然限制在低于内置电位（二极管压降）。 为了满足需要与驱动到更高电压电平的外部电路接口的某些应用，本发明包括在与JFET器件相同的衬底上构建CMOS器件的结构和方法。

    JFET Having a Step Channel Doping Profile and Method of Fabrication
    9.
    发明申请
    JFET Having a Step Channel Doping Profile and Method of Fabrication 审中-公开
    具有阶跃通道掺杂曲线和制造方法的JFET

    公开(公告)号：US20090137088A1

    公开(公告)日：2009-05-28

    申请号：US12362920

    申请日：2009-01-30

    申请人： Sachin R. Sonkusale ,  Weimin Zhang ,  Ashok K. Kapoor

    发明人： Sachin R. Sonkusale ,  Weimin Zhang ,  Ashok K. Kapoor

    IPC分类号： H01L21/337

    CPC分类号： H01L29/1058 ,  H01L29/66901 ,  H01L29/808

    摘要： A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.

    摘要翻译： 结型场效应晶体管包括半导体衬底，形成在衬底中的源极区，形成在衬底中并与源极区隔开的漏极区和形成在衬底中的栅极区。 晶体管还包括形成在衬底中并与栅极区隔开的第一沟道区，以及形成在衬底中以及在第一沟道区和栅极区之间的第二沟道区。 第二沟道区具有比第一沟道区更高的掺杂杂质浓度。

    Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom
    10.
    发明申请
    Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom 审中-公开
    将应力层应用于其上形成的半导体器件和器件的方法

    公开(公告)号：US20090072278A1

    公开(公告)日：2009-03-19

    申请号：US12272416

    申请日：2008-11-17

    申请人： Ashok K. Kapoor

    发明人： Ashok K. Kapoor

    IPC分类号： H01L29/808 ,  H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/66901

    摘要： A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

    摘要翻译： 半导体器件包括半导体材料的衬底。 半导体器件的源极区域，漏极区域和导电区域形成在衬底中并且掺杂有第一类型的杂质。 当半导体器件工作在导通状态时，导电区域可操作以在漏极区域和源极区域之间传导电流。 栅极区也形成在衬底中并掺杂有第二类杂质。 栅极区域邻接导电区域的沟道区域。 应力层沉积在导电区域的至少一部分上。 应力层沿着导电区域的至少一部分导电区域的边界沿着导电区域施加应力。