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    Automating photolithography in the fabrication of integrated circuits
    1.
    发明授权
    Automating photolithography in the fabrication of integrated circuits 失效
    在制造集成电路时自动化光刻

    公开(公告)号：US5663076A

    公开(公告)日：1997-09-02

    申请号：US512678

    申请日：1995-08-08

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Automating photolithography in the fabrication of integrated circuits
    2.
    发明授权
    Automating photolithography in the fabrication of integrated circuits 失效
    在制造集成电路时自动化光刻

    公开(公告)号：US06418353B1

    公开(公告)日：2002-07-09

    申请号：US09064802

    申请日：1998-04-22

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G06F1900

    CPC分类号： G03F7/705 ,  G03F7/70433 ,  G03F7/70625

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 制造数据包括流程和。 然后将产量参数转移回瑞利处理器用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Process for forming low dielectric constant insulation layer on integrated circuit structure
    3.
    发明授权
    Process for forming low dielectric constant insulation layer on integrated circuit structure 失效
    在集成电路结构上形成低介电常数绝缘层的工艺

    公开(公告)号：US5393712A

    公开(公告)日：1995-02-28

    申请号：US84829

    申请日：1993-06-28

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L21/02304 ,  H01L21/02129 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02343 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76829 ,  H01L2221/1047

    摘要： A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material. The second liquid is then preferably removed from the matrix-forming material either by lyophilizing (freeze drying) or by raising the pressure and temperature above the critical point of the second liquid.

    摘要翻译： 描述了一种用于在半导体晶片上的集成电路结构上形成低介电常数绝缘层的工艺，首先在集成电路结构上形成复合层，该复合层包括一种或多种可提取材料和一种或多种矩阵形成绝缘材料 半导体晶片，然后从基质形成材料中选择性地除去可提取材料，而不损坏剩余的基体材料，从而留下绝缘材料的多孔基体。 在一个实施方案中，复合层由凝胶形成。 通过首先将其溶解在不是基质形成材料的溶剂形成溶液的第一液体中来除去可萃取材料。 然后通过在与第一溶剂混溶的第二液体中冲洗基质并且也不是基质形成材料的溶剂，从基质形成材料中除去该溶液。 然后优选通过冻干（冷冻干燥）或通过将压力和温度升高到高于第二液体的临界点的方式从基质形成材料中除去第二液体。

    Automating photolithography in the fabrication of integrated circuits
    4.
    再颁专利
    Automating photolithography in the fabrication of integrated circuits 有权
    在制造集成电路时自动化光刻

    公开(公告)号：USRE38900E1

    公开(公告)日：2005-11-29

    申请号：US09273171

    申请日：1999-03-19

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Hexagonal DRAM array
    8.
    发明授权
    Hexagonal DRAM array 失效
    六角形DRAM阵列

    公开(公告)号：US5742086A

    公开(公告)日：1998-04-21

    申请号：US517153

    申请日：1995-08-21

    申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

    发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

    IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/78 ,  H01L29/41

    CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

    摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

    摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

    Programmable triangular shaped device having variable gain
    9.
    发明授权
    Programmable triangular shaped device having variable gain 失效
    具有可变增益的可编程三角形器件

    公开(公告)号：US06312980B1

    公开(公告)日：2001-11-06

    申请号：US09092827

    申请日：1998-06-05

    申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriv B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

    发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriv B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

    IPC分类号： H01L2182

    CPC分类号： H01L27/108 ,  G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/528 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H01L29/0657 ,  H01L2924/0002 ,  Y10S438/965 ,  H01L2924/00

    摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

    摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。