Processor with scheduler architecture supporting multiple distinct scheduling algorithms
    1.
    发明申请
    Processor with scheduler architecture supporting multiple distinct scheduling algorithms 有权
    具有调度器架构的处理器,支持多种不同的调度算法

    公开(公告)号:US20050111461A1

    公开(公告)日:2005-05-26

    申请号:US10722933

    申请日:2003-11-26

    IPC分类号: H04L12/56

    摘要: A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm. Association of a given one of the transmission elements with a particular one of the second table entries establishes a scheduling rate for that transmission element. The scheduler maintains a second table pointer identifying a current one of the second table entries that is eligible for transmission.

    摘要翻译: 处理器包括调度器,其利用至少第一表和第二表来调度用于从多个队列或其他传输元件传输的数据块。 第一表可以包括对应于根据第一调度算法(例如加权公平排队调度算法)对数据块进行调度的传输元件的条目的至少第一和第二先进先出(FIFO)列表 。 调度器维护第一表指针,其将第一表的第一列表和第二列表中的至少一个列表标识为优先于第一表的第一和第二列表中的另一列。 第二表包括对应于根据诸如恒定比特率或可变比特率调度算法的第二调度算法对其数据块进行调度的传输元件的多个条目。 给定一个传输单元与特定的一个第二表项的关联建立该传输单元的调度速率。 调度器维护第二表指针,其标识有资格传输的第二表条目中的当前一个。

    Link layer device with non-linear polling of multiple physical layer device ports
    2.
    发明申请
    Link layer device with non-linear polling of multiple physical layer device ports 有权
    具有多个物理层设备端口的非线性轮询的链路层设备

    公开(公告)号:US20050169298A1

    公开(公告)日:2005-08-04

    申请号:US10768764

    申请日:2004-01-30

    IPC分类号: H04L12/24 H04L12/403

    CPC分类号: H04L41/00

    摘要: In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.

    摘要翻译: 在包括可连接到一个或多个物理层设备的链路层设备的通信系统中,一个或多个物理层设备的多个端口中的至少一个给定的一个被指定为要由其请求状态信息的端口 对于多个端口中的一个或多个其他端口,要求比这种信息更频繁的链路层设备。 然后根据非线性轮询序列由链路层设备轮询端口,使得至少一个指定端口比一个或多个其他端口更频繁地轮询。 指定端口可以包括链路层设备结合当前数据传输发送数据的端口。 因此,可以基于在通信系统中的链路层设备和物理层设备之间发生的特定数据传输来动态地改变非线性轮询序列。

    Link layer device with configurable address pin allocation
    3.
    发明申请
    Link layer device with configurable address pin allocation 有权
    链路层设备具有可配置的地址引脚分配

    公开(公告)号:US20050138259A1

    公开(公告)日:2005-06-23

    申请号:US10744567

    申请日:2003-12-23

    IPC分类号: G06F13/14 G06F13/38

    CPC分类号: G06F13/385

    摘要: Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

    摘要翻译: 公开了用于将接口总线的地址引脚灵活分配给接口总线的特定子总线的技术。 接口总线在通信系统中的至少一个物理层设备和链路层设备之间。 每个子总线具有与其相关联的链路层设备的接口块,该接口总线可配置为承载具有多个部分的复合地址信号,每个部分与接口总线的一个地址引脚相关联。 控制链路层设备的接口块,使得接口块的至少一个子集中的每一个仅使用根据存储在链路层中的配置信息可控地分配给相关联的子总线的特定地址引脚 设备。 复合地址信号作为接口块的地址输出的组合生成。

    Selectively doped semi-conductors and methods of making the same
    5.
    发明授权
    Selectively doped semi-conductors and methods of making the same 有权
    选择性掺杂半导体及其制造方法

    公开(公告)号:US09059081B2

    公开(公告)日:2015-06-16

    申请号:US12442953

    申请日:2007-11-13

    摘要: The present invention is generally directed to methods of selectively doping a substrate and the resulting selectively doped substrates. The methods include doping an epilayer of a substrate with the selected doping material to adjust the conductivity of either the epilayers grown over a substrate or the substrate itself. The methods utilize lithography to control the location of the doped regions on the substrate. The process steps can be repeated to form a cyclic method of selectively doping different areas of the substrate with the same or different doping materials to further adjust the properties of the resulting substrate.

    摘要翻译: 本发明一般涉及选择性掺杂衬底和所得到的选择性掺杂衬底的方法。 所述方法包括用所选择的掺杂材料掺杂衬底的外延层以调节在衬底或衬底本身上生长的外延层的导电性。 该方法利用光刻来控制衬底上的掺杂区域的位置。 可以重复工艺步骤以形成用相同或不同的掺杂材料选择性地掺杂衬底的不同区域以进一步调节所得衬底的性质的循环方法。

    High power ultraviolet light sources and method of fabricating the same
    6.
    发明授权
    High power ultraviolet light sources and method of fabricating the same 有权
    大功率紫外光源及其制造方法

    公开(公告)号:US08680551B1

    公开(公告)日:2014-03-25

    申请号:US13070174

    申请日:2011-03-23

    IPC分类号: H01L33/60

    摘要: A vertically conducting LED comprising, in a layered arrangement: a highly thermally conductive submount wherein the highly conductive submount has a thermal conductivity of at least 100 W/m0K; a p-type layer comprising Al1-x-yInyGax N wherein 0≦x≦1 and 0≦y≦1; a quantum well layer comprising Al1-x-yInyGaxN wherein 0≦x≦1 and 0≦y≦1; an n-type layer comprising Al1-x-yInyGaxN wherein 0≦x≦1 and 0≦y≦1; and an n-type contact layer wherein the LED has a peak emission at 200-365 nm.

    摘要翻译: 一种垂直导电LED,其包括:分层布置:高导热基座,其中所述高导电基座具有至少100W / m0K的热导率; 包含Al1-x-yInyGax N的p型层,其中0≦̸ x≦̸ 1和0& nlE; y≦̸ 1; 包含Al1-x-yInyGaxN的量子阱层,其中0和nlE; x和nlE; 1和0& nlE; y≦̸ 1; 包含Al1-x-yInyGaxN的n型层,其中0≦̸ x≦̸ 1和0< nlE; y≦̸ 1; 和n型接触层,其中LED在200-365nm处具有峰值发射。

    Ultraviolet light emitting diode with AC voltage operation
    7.
    发明授权
    Ultraviolet light emitting diode with AC voltage operation 有权
    具有交流电压工作的紫外线发光二极管

    公开(公告)号:US08507941B2

    公开(公告)日:2013-08-13

    申请号:US12997240

    申请日:2009-06-06

    IPC分类号: H01L33/00

    摘要: Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and a second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over a strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.

    摘要翻译: 紫外线发光照明器及其制造方法包括紫外发光二极管阵列和第一和第二终端阵列。 当跨越第一和第二端子以及因此施加到每个二极管的交流电时,照明器以与交流电流相对应的频率发射紫外光。 照明器包括具有紫外光发射量子阱的模板,具有第一类型导电性的第一缓冲层和具有第二导电类型的第二缓冲层,所有这些均优选沉积在应变消除层上。 将第一和第二金属接触分别施加到具有第一和第二导电类型的半导体层以完成LED。 发射光谱范围为190nm至369nm。 照明器可以被配置成各种材料,几何形状,尺寸和设计。

    Digital oxide deposition of SiO2 layers on wafers
    8.
    发明授权
    Digital oxide deposition of SiO2 layers on wafers 有权
    SiO 2层在晶片上的数字氧化沉积

    公开(公告)号:US08372697B2

    公开(公告)日:2013-02-12

    申请号:US11800712

    申请日:2007-05-07

    IPC分类号: H01L21/20

    摘要: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.

    摘要翻译: 通常公开了新的二氧化硅和氮化硅沉积方法。 在一个实施例中,该方法包括在温度在约65℃至约350℃之间的衬底的表面上沉积硅。加热的衬底暴露于基本上不含氧化剂的硅源。 然后用基本上不含硅源的氧源氧化表面上的硅。 作为氧化硅的结果,在衬底的表面上形成氧化硅层。 或者,或另外,可以提供氮源以在衬底的表面上产生氮化硅。

    VERTICAL DEEP ULTRAVIOLET LIGHT EMITTING DIODES
    10.
    发明申请
    VERTICAL DEEP ULTRAVIOLET LIGHT EMITTING DIODES 有权
    垂直深紫外线发光二极管

    公开(公告)号:US20120034718A1

    公开(公告)日:2012-02-09

    申请号:US13226806

    申请日:2011-09-07

    申请人: Asif Khan

    发明人: Asif Khan

    IPC分类号: H01L33/48 H01L33/22

    摘要: A vertical geometry light emitting diode with a strain relieved superlattice layer on a substrate comprising doped AlXInYGa1-X-YN. A first doped layer is on the strain relieved superlattice layer AlXInYGa1-X-YN and the first doped layer has a first conductivity. A multilayer quantum well is on the first doped layer comprising alternating layers quantum wells and barrier layers. The multilayer quantum well terminates with a barrier layer on each side thereof. A second doped layer is on the quantum well wherein the second doped layer comprises AlXInYGa1-X-YN and said second doped layer has a different conductivity than said first doped layer. A contact layer is on the third doped layer and the contact layer has a different conductivity than the third doped layer. A metallic contact is in a vertical geometry orientation.

    摘要翻译: 在包含掺杂的AlXInYGa1-X-YN的衬底上具有应变消除的超晶格层的垂直几何形状发光二极管。 第一掺杂层位于应变消除的超晶格层AlXInYGa1-X-YN上,第一掺杂层具有第一导电性。 多层量子阱在第一掺杂层上,包括交替层量子阱和势垒层。 多层量子阱在其每一侧终止阻挡层。 第二掺杂层在量子阱上,其中第二掺杂层包含AlXInYGa1-X-YN,而所述第二掺杂层具有与所述第一掺杂层不同的导电性。 接触层在第三掺杂层上,并且接触层具有与第三掺杂层不同的导电性。 金属接触处于垂直几何取向。