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    SPLIT GATE NON-VOLATILE MEMORY CELL
    1.
    发明申请
    SPLIT GATE NON-VOLATILE MEMORY CELL 有权
    分离门非挥发性记忆细胞

    公开(公告)号：US20150035034A1

    公开(公告)日：2015-02-05

    申请号：US13954205

    申请日：2013-07-30

    申请人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    发明人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    IPC分类号： H01L29/66 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

    摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。

    Split gate non-volatile memory cell
    2.
    发明授权
    Split gate non-volatile memory cell 有权
    分闸门非易失性存储单元

    公开(公告)号：US08962416B1

    公开(公告)日：2015-02-24

    申请号：US13954205

    申请日：2013-07-30

    申请人： Brian A. Winstead ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    发明人： Brian A. Winstead ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

    摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。

    METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY
    3.
    发明申请
    METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY 有权
    形成具有改进的可靠性的分离器存储器的方法

    公开(公告)号：US20160035848A1

    公开(公告)日：2016-02-04

    申请号：US14446796

    申请日：2014-07-30

    申请人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

    发明人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

    IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L29/08 ,  H01L21/265 ,  H01L29/10 ,  H01L29/788 ,  H01L29/66

    CPC分类号： H01L29/42328 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

    摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

    摘要翻译： 第一掺杂区域从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区域从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。

    Method of forming split gate memory with improved reliability
    4.
    发明授权
    Method of forming split gate memory with improved reliability 有权
    形成具有改进的可靠性的分闸门存储器的方法

    公开(公告)号：US09397176B2

    公开(公告)日：2016-07-19

    申请号：US14446796

    申请日：2014-07-30

    申请人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

    发明人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

    IPC分类号： H01L21/8239 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08 ,  H01L29/41

    CPC分类号： H01L29/42328 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

    摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

    摘要翻译： 第一掺杂区从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。

    Stressed semiconductor device and method for making
    5.
    发明授权
    Stressed semiconductor device and method for making 有权
    强调半导体器件及其制造方法

    公开(公告)号：US07821055B2

    公开(公告)日：2010-10-26

    申请号：US12414763

    申请日：2009-03-31

    申请人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

    发明人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

    摘要翻译： 在半导体层上制造半导体器件的方法包括在栅极电介质上形成栅极电介质和栅极材料的第一层。 第一层被蚀刻以在半导体层的第一部分上移除第一层栅极材料的一部分并留下选择栅极部分。 存储层形成在选择栅极部分上方和半导体层的第一部分之上。 在存储层上形成第二层栅极材料层。 第二层栅极材料被蚀刻以在选择栅极部分的第一部分上移除第二层栅极材料的第一部分。 选择栅极的第一部分的一部分被蚀刻以留下L形选择结构。 结果是具有L形选择栅极的存储单元。

    Method of making a semiconductor structure useful in making a split gate non-volatile memory cell
    7.
    发明授权
    Method of making a semiconductor structure useful in making a split gate non-volatile memory cell 有权
    制造半导体结构的方法，其用于制造分离栅极非易失性存储单元

    公开(公告)号：US07985649B1

    公开(公告)日：2011-07-26

    申请号：US12683972

    申请日：2010-01-07

    申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

    摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL
    8.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL 有权
    制造分裂栅非挥发性记忆细胞的半导体结构的方法

    公开(公告)号：US20110165749A1

    公开(公告)日：2011-07-07

    申请号：US12683972

    申请日：2010-01-07

    申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

    摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

    STRESSED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING
    9.
    发明申请
    STRESSED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING 有权
    应力半导体器件及其制造方法

    公开(公告)号：US20100244121A1

    公开(公告)日：2010-09-30

    申请号：US12414763

    申请日：2009-03-31

    申请人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

    发明人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

    摘要翻译： 在半导体层上制造半导体器件的方法包括在栅极电介质上形成栅极电介质和栅极材料的第一层。 第一层被蚀刻以在半导体层的第一部分上移除第一层栅极材料的一部分并留下选择栅极部分。 存储层形成在选择栅极部分上方和半导体层的第一部分之上。 在存储层上形成第二层栅极材料层。 第二层栅极材料被蚀刻以在选择栅极部分的第一部分上去除第二层栅极材料的第一部分。 选择栅极的第一部分的一部分被蚀刻以留下L形选择结构。 结果是具有L形选择栅极的存储单元。