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公开(公告)号：US20150035034A1
公开(公告)日：2015-02-05
申请号：US13954205
申请日：2013-07-30
IPC分类号： H01L29/66 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。
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公开(公告)号：US08962416B1
公开(公告)日：2015-02-24
申请号：US13954205
申请日：2013-07-30
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。
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公开(公告)号：US09397176B2
公开(公告)日：2016-07-19
申请号：US14446796
申请日：2014-07-30
IPC分类号： H01L21/8239 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/66 , H01L21/265 , H01L29/10 , H01L29/08 , H01L29/41
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
摘要翻译： 第一掺杂区从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。
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公开(公告)号：US20160035848A1
公开(公告)日：2016-02-04
申请号：US14446796
申请日：2014-07-30
IPC分类号： H01L29/423 , H01L29/792 , H01L29/08 , H01L21/265 , H01L29/10 , H01L29/788 , H01L29/66
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
摘要翻译： 第一掺杂区域从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区域从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。
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公开(公告)号：US09685339B2
公开(公告)日：2017-06-20
申请号：US13873917
申请日：2013-04-30
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L27/11521
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332
摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.
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公开(公告)号：US09219167B2
公开(公告)日：2015-12-22
申请号：US14135142
申请日：2013-12-19
IPC分类号： H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/3105 , H01L21/321 , H01L29/66 , H01L29/423 , H01L21/28
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/31055 , H01L21/3212 , H01L21/32133 , H01L21/32139 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。
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公开(公告)号：US20150179816A1
公开(公告)日：2015-06-25
申请号：US14135142
申请日：2013-12-19
IPC分类号： H01L29/792 , H01L21/3105 , H01L21/321 , H01L21/28 , H01L29/423 , H01L29/51 , H01L29/49 , H01L21/3213 , H01L29/66
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/31055 , H01L21/3212 , H01L21/32133 , H01L21/32139 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。
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公开(公告)号：US09006093B2
公开(公告)日：2015-04-14
申请号：US13928666
申请日：2013-06-27
申请人： Cheong Min Hong , Sung-Taeg Kang , Jane A. Yater
发明人： Cheong Min Hong , Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L29/788 , H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L27/11529 , H01L27/11546 , H01L29/42328 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.
摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。
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公开(公告)号：US09082650B2
公开(公告)日：2015-07-14
申请号：US13971987
申请日：2013-08-21
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/11534 , H01L29/42332 , H01L29/66545 , H01L29/66825
摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.
摘要翻译： 制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。 间隔选择栅极通过沉积保形层，随后进行回蚀而形成。 图案化蚀刻导致将电荷存储层的一部分留在选择栅上。 形成在逻辑区域中的虚拟栅极结构具有由绝缘层包围的虚拟栅极。 执行化学抛光导致电荷存储层的顶表面与虚拟栅极结构的顶表面共面。 用包括另外的化学机械抛光的金属逻辑门来替代虚拟栅极结构的一部分导致电荷存储层的顶表面与金属逻辑门共面。
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10.发明授权Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays 有权在分闸门非易失性存储器（NVM）单元阵列中形成接触着陆区域的方法公开(公告)号：US09054208B2
公开(公告)日：2015-06-09
申请号：US14022646
申请日：2013-09-10
申请人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L21/3205 , H01L29/788 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
摘要翻译： 公开了用于在分闸NVM（非易失性存储器）系统中形成接触着陆区域的方法和相关结构。 形成虚拟选择栅结构，同时形成分闸NVM单元的选择栅极。 在选择栅极和虚拟选择栅极结构上形成控制栅极层，以及中间电荷存储层。 控制栅极材料将填充选择栅极材料和虚拟选择栅极材料之间的间隙。 然后使用非图案化间隔物蚀刻来蚀刻控制栅极层以形成与虚拟选择栅极结构相关联的接触着色区域，同时还形成用于分离栅极NVM单元的间隔物控制栅极。 所公开的实施例提供改进的（例如更平坦的）接触着陆区域，而不需要额外的处理步骤，而不增加所得到的NVM单元阵列的间距。
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