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公开(公告)号：US5151383A
公开(公告)日：1992-09-29
申请号：US307154
申请日：1989-02-06
CPC分类号： H01L33/18 , C23C16/24 , C23C16/46 , C23C16/463 , H01L33/0012 , H01L33/0033 , H01L33/0058
摘要： A method is described for fabricating electroluminescent devices exhibiting visible electroluminescence at room temperature, where the devices include at least one doped layer of amorphous hydrogenated silicon (a-Si:H). The a-Si:H layer is deposited on a substrate by homogeneous chemical vapor deposition (H-CVD) in which the substrate is held at a temperature lower than about 200.degree. C. and the a-Si:H layer is doped in-situ during deposition, the amount of hydrogen incorporated in the deposited layer being 12-50 atomic percent. The bandgap of the a-Si:H layer is between 1.6 and 2.6 eV, and in preferrable embodiments is between 2.0 and 2.6 eV. The conductivity of the a-Si:H layer is chosen in accordance with device requirements, and can be 10.sup.16 -10.sup.19 carriers/cm.sup.2. The bandgap of the a-Si:H layer depends at least in part on the temperature of the substrate on which the layer is deposited, and can be "tuned" by changing the substrate temperature.
摘要翻译： 描述了一种用于制造在室温下显示可见电致发光的电致发光器件的方法，其中器件包括至少一个非晶氢化硅掺杂层（a-Si：H）。 通过均匀化学气相沉积（H-CVD）将a-Si：H层沉积在衬底上，其中衬底保持在低于约200℃的温度，并且a-Si：H层被掺杂在 在沉积期间原位，沉积层中掺入的氢的量为12-50原子％。 a-Si：H层的带隙在1.6和2.6eV之间，优选的实施方案是在2.0和2.6eV之间。 a-Si：H层的电导率根据器件要求选择，可以为1016-1019载体/ cm2。 a-Si：H层的带隙至少部分取决于沉积该层的衬底的温度，并且可以通过改变衬底温度“调谐”。
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公开(公告)号：US4684542A
公开(公告)日：1987-08-04
申请号：US895119
申请日：1986-08-11
CPC分类号： C23C16/42 , H01L21/28061
摘要： A process for preparing tungsten silicide films using low pressure, low temperature chemical vapor deposition to deposit silicon-rich tungsten silicide films. As a source of silicon, higher order silanes, such as disilane and trisilane, are used. The gaseous tungsten source is WF.sub.6. The substrate temperature range is less than about 370.degree. C., while the total pressure range is in the range 0.05-1 Torr. WF.sub.6 flow rates are generally less than 25 sccm, while the higher order silane flow rates are generally less than about 400 sccm.
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公开(公告)号：US4592933A
公开(公告)日：1986-06-03
申请号：US626504
申请日：1984-06-29
IPC分类号： H01L21/205 , C23C16/44 , C23C16/455 , C30B25/14 , C23C16/00 , C23C16/30
CPC分类号： C23C16/4557 , C23C16/45514 , C23C16/4558 , C30B25/14
摘要： A technique and apparatus for homogeneous chemical vapor deposition (HCVD), wherein a heated carrier gas is mixed with a source gas in a location close to a substrate on which deposition is to occur. The heated carrier gas transfers heat to the source gas in order to decompose it, producing the intermediate species necessary for deposition onto the substrate. Thus, the source gas is not subjected to heating above its pyrolysis temperature prior to being transported to the immediate vicinity of the substrate. This HCVD apparatus includes a heat source for heating the carrier gas, a tube for bringing the heated carrier gas to a location close to the substrate, and another tube for bringing the reactive source gas to the aforementioned location where it is mixed with the hot carrier gas to cause decomposition of the source gas close to the substrate. The substrate temperature is decoupled from the hot gas temperature and is significantly colder than the hot gas temperature. Simultaneous deposition onto a plurality of substrates is possible, and the system can be scaled-up to provide deposition over a large area.
摘要翻译： 一种用于均匀化学气相沉积（HCVD）的技术和装置，其中将加热的载气与源气体混合在靠近其上沉积的基底的位置。 加热的载气将热量转移到源气体以便分解，产生沉积到基底上所需的中间物质。 因此，在将其输送到基板的紧邻附近之前，源气体不经受高于其热解温度的加热。 该HCVD装置包括用于加热载气的热源，用于将加热的载气引导到靠近基板的位置的管，以及用于将反应源气体引导到与热载体混合的上述位置的另一管 气体导致源气体靠近基板的分解。 衬底温度与热气体温度分离，并且比热气体温度明显更冷。 同时沉积到多个基板上是可能的，并且该系统可以放大以在大面积上提供沉积。
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公开(公告)号：US5273829A
公开(公告)日：1993-12-28
申请号：US774010
申请日：1991-10-08
IPC分类号： G01L9/00 , G03F1/22 , H01L21/027 , H01L21/20 , H01L21/205 , H01L21/306 , G03G5/14
CPC分类号： G03F1/22 , G01L9/0042 , H01L21/30608
摘要： The subject invention provides a silicon membrane material made from silicon that is epitaxially deposited at low temperatures greater than or equal to 500.degree. C. and doped with controlled amounts of boron and germanium. A silicon membrane structure is provided and made by one or more layers of ultra thin epitaxially deposited silicon layers that are precisely controlled in both thickness and composition. At least one of the layers is doped with boron in a concentration range greater than 2.times.10.sup.20 atoms of boron per cubic centimeter of silicon, or with germanium in a concentration range greater than 5.times.10.sup.20 atoms of germanium per cubic centimeter of silicon, or with a combination of boron and germanium in these concentration ranges. A silicon membrane fabrication process is also provided which requires no additional masking film to protect the membrane surface during KOH etching of the bulk silicon substrate.
摘要翻译： 本发明提供了由硅制成的硅膜材料，其在大于或等于500℃的低温下外延沉积，并掺杂受控量的硼和锗。 硅膜结构由一层或多层超薄外延沉积的硅层提供并制成，其在厚度和组成上精确控制。 这些层中的至少一层掺杂了硼，其浓度范围大于每立方厘米硅的2×1020个原子的硼，或者锗浓度范围大于每立方厘米硅的5×1020原子，或者与 硼和锗在这些浓度范围内。 还提供了硅膜制造方法，其不需要额外的掩模膜来在体硅衬底的KOH蚀刻期间保护膜表面。
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公开(公告)号：US5159508A
公开(公告)日：1992-10-27
申请号：US634671
申请日：1990-12-27
CPC分类号： G11B5/6005 , G11B5/3106 , Y10T29/49041
摘要： A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer and a thin layer of amorphous hydrogenated carbon. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.
摘要翻译： 一种在其轨道上具有保护涂层的磁头滑块，保护涂层包括薄粘合层和非晶氢化碳薄层。 在将薄膜磁头研磨成选定的尺寸之后，但是在空气轴承表面上产生轨道图案之前，保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头，并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。
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公开(公告)号：US4972246A
公开(公告)日：1990-11-20
申请号：US171603
申请日：1988-03-22
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/15 , H01L29/161 , H01L29/201 , H01L29/737
CPC分类号： H01L29/157 , H01L29/1004
摘要： A homojunction bipolar transistor having a superlattice base region comprising alternate layers of extrinsic and intrinsic layers, with extrinsic layers being of the opposite conductivity of the emitter and collector layers of the transistor. The alternate extrinsic and intrinsic layers have substantially different doping levels providing abrupt transitions in the valence and conduction bands between layers. The abrupt transitions result in the energy band gap in the base region being effectively reduced with respect to the band gap in the emitter region. In one embodiment, the effective narrow band gap base transistor is implemented by converting a portion of the upper layers of the superlattice to a homogeneous region by heavily doping the portion to form the emitter of the transistor.
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7.发明授权
公开(公告)号：US4504331A
公开(公告)日：1985-03-12
申请号：US559583
申请日：1983-12-08
IPC分类号： H01L21/205 , H01L21/322
CPC分类号： H01L21/0262 , H01L21/02546 , H01L21/02576 , Y10S252/951 , Y10S438/925
摘要： In intermetallic semiconductor crystal growth such as the growth of GaAs and GaAlAs, silicon as a dopant can be introduced more efficiently and evenly when provided as a gaseous hydride based compound involving a molecule where there are joined silicon atoms such as Si.sub.2 H.sub.6 to Si.sub.5 H.sub.12.
摘要翻译： 在诸如GaAs和GaAlAs的生长的金属间半导体晶体生长中，作为掺杂剂的硅可以作为包含分子的气态氢化物基化合物而被更有效和均匀地引入，其中存在诸如Si 2 H 6至Si 5 H 12的硅原子的分子。
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8.发明授权Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers 失效用于外延硅层的低温，低压化学气相沉积的方法和装置
公开(公告)号：US5607511A
公开(公告)日：1997-03-04
申请号：US186195
申请日：1994-01-24
申请人： Bernard S. Meyerson
发明人： Bernard S. Meyerson
IPC分类号： C23C16/24 , C23C16/44 , C30B25/14 , H01L21/205 , C23C16/00
CPC分类号： H01L21/02381 , C23C16/24 , C23C16/4405 , C23C16/4412 , C30B25/14 , H01L21/02532 , H01L21/0262
摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree. C., and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of about 10.sup.-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.
摘要翻译： 描述了一种用于在热壁中的多个基板上沉积单晶硅外延膜的方法和装置，等温沉积系统。 沉积温度低于约800℃，并且沉积期间的操作压力使得非平衡生长动力学决定了硅膜的沉积。 产生硅的等温浴气，允许在多个基板上同时沉积外延硅膜。 这是一种流程系统，其中提供了用于在外延沉积之前建立在约10-9乇范围内的超高真空度的装置。 外延硅层可以原位掺杂以提供非常突然限定的n型或p型导电性区域。
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公开(公告)号：US5319240A
公开(公告)日：1994-06-07
申请号：US12812
申请日：1993-02-03
CPC分类号： H01L27/0688
摘要： A set of three-dimensional structures and devices may be wired together to perform a wide variety of circuit functions such as SRAMs, DRAMs, ROMs and PLAs. Both N-Channel and P-Channel transistors can be made. The P-channel devices are fabricated conventionally in separate N-wells or, alternatively, they are constructed in a like manner to the array N-channel devices. N and P diffused wire can be electrically joined at polysilicon contacts.
摘要翻译： 一组三维结构和器件可以连接在一起以执行各种各样的电路功能，例如SRAM，DRAM，ROM和PLA。 可以制造N沟道和P沟道晶体管。 P沟道器件通常在单独的N阱中制造，或者替代地，它们以类似的方式构造到阵列N沟道器件。 N和P扩散线可以在多晶硅接触处电连接。
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10.发明授权
公开(公告)号：US5117271A
公开(公告)日：1992-05-26
申请号：US624018
申请日：1990-12-07
申请人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.
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