公开(公告)号：US20050023642A1

公开(公告)日：2005-02-03

申请号：US10496531

申请日：2002-12-02

申请人： Bernd Heinemann ,  Dieter Knoll ,  Karl-Ernst Ehwald ,  Holger Rucker

发明人： Bernd Heinemann ,  Dieter Knoll ,  Karl-Ernst Ehwald ,  Holger Rucker

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7325

摘要： The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

摘要翻译： 根据本发明的半导体器件包括衬底，限定半导体衬底的有源区域的场绝缘区域，集电极，与集电极相关联的至少一个集电极接触区域以及具有相关联的基极连接区域的基极。 集电极和集电极接触区形成在相同的有源区中。 此外，基极连接区部分地延伸在有源区上方并且通过绝缘体层与有源区的表面分离。

公开(公告)号：US06878995B2

公开(公告)日：2005-04-12

申请号：US10239933

申请日：2001-03-24

申请人： Karl-Ernst Ehwald ,  Bernd Heinemann ,  Dieter Knoll ,  Wolfgang Winkler

发明人： Karl-Ernst Ehwald ,  Bernd Heinemann ,  Dieter Knoll ,  Wolfgang Winkler

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/66659 ,  H01L29/0615 ,  H01L29/1033 ,  H01L29/7835

摘要： A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-μm production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

摘要翻译： 可以通过适当的布局配置来设计CMOS兼容的DMOS晶体管，用于非常高的漏极电压或在非常高的频率下进行功率放大，并且可以以与常规子母线相比低的额外成本来生产CMOS兼容的DMOS晶体管 CMOS电路的生产技术。 在电流流过的整个（有源）区域中，晶体管的栅极绝缘体在控制栅极下方具有整体厚度。 靠近表面并确定晶体管阈值电压的增加的掺杂浓度（阱区）的区域被布置在控制栅极下方，其占据位于有源区上的控制栅极下方的整个区域并且结束于其中 在控制栅极和高掺杂漏极区之间的偏移漂移空间。 漂移空间的整个表面由漏区（VLDD）的导电类型的区域覆盖，其与高掺杂漏极区相比被低掺杂。

公开(公告)号：US08035167B2

公开(公告)日：2011-10-11

申请号：US12448032

申请日：2007-12-07

申请人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

发明人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

IPC分类号： H01L27/015

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的浅的场绝缘区域比有源双极晶体管区域的第一深度方向的第二较深的深度方向的区域限定有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。

公开(公告)号：US20100019326A1

公开(公告)日：2010-01-28

申请号：US12448032

申请日：2007-12-07

申请人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

发明人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的第二类型的浅的场绝缘区域比有源双极性晶体管区域的第一深度方向的第二较深的深度方向的区域限定了观察到的有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。

公开(公告)号：US06465318B1

公开(公告)日：2002-10-15

申请号：US09787571

申请日：2001-08-02

申请人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

发明人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.

摘要翻译： 本发明涉及双极晶体管及其制造方法。 本发明的任务是提出一种双极晶体管及其制造方法，其消除了用于制造基底的具有差分外延的简单多晶硅技术的常规布置的缺点， 双极晶体管的速度特性，以在金属触点和有源（内部）晶体管区域之间产生高导电连接以及最小化的无源晶体管表面，同时避免任何额外的工艺复杂性和增加的接触电阻。 本发明解决了通过创建合适的外延工艺条件的工作，多晶硅层以比有源晶体管区中的外延层更大的厚度沉积在绝缘体区上。 与外延层相比，多晶硅层的厚度越大，通过使用非常低的温度来沉积一部分或整个缓冲层来实现。 使用低温进行沉积允许绝缘体层的更好的成核和减少沉积的空闲时间。 与有源晶体管区域相比，这允许在绝缘体层上实现更大的厚度。

公开(公告)号：US07595534B2

公开(公告)日：2009-09-29

申请号：US10433969

申请日：2001-12-06

申请人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll ,  Bernd Tillack ,  Dirk Wolansky ,  Peter Schley

发明人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll ,  Bernd Tillack ,  Dirk Wolansky ,  Peter Schley

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/74 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

摘要： The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.

摘要翻译： 本发明涉及衬底晶片中的层。 本发明的目的是提供衬底晶片中的层，其中克服了常规组件的缺点，以便一方面实现具有相对较低成本的高度缩放的数字CMOS电路中的闩锁的适当电阻，以及 另一方面，为了确保模拟高频电路的低衬底损耗/耦合，此外，以非破坏性的方式影响组件行为。 为此，本发明提供了在具有一个或多个掩埋的高碳Si层（3）的外延层和Si覆盖层（4）下的高电阻p-Si衬底（2）中的注入剂量， 与传统的基板晶片相比，通过抑制掺杂剂扩散以及在补偿注入缺陷时产生缺陷而用于逆向槽型材，从而实现了谷电阻的降低，最后增加了电阻 闭锁

公开(公告)号：US07323390B2

公开(公告)日：2008-01-29

申请号：US10496531

申请日：2002-12-02

申请人： Bernd Heinemann ,  Dieter Knoll ,  Karl-Ernst Ehwald ,  Holger Rücker

发明人： Bernd Heinemann ,  Dieter Knoll ,  Karl-Ernst Ehwald ,  Holger Rücker

IPC分类号： H01L21/31

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7325

摘要： The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

摘要翻译： 根据本发明的半导体器件包括衬底，限定半导体衬底的有源区域的场绝缘区域，集电极，与集电极相关联的至少一个集电极接触区域以及具有相关联的基极连接区域的基极。 集电极和集电极接触区形成在相同的有源区中。 此外，基极连接区部分地延伸到有源区上方并且通过绝缘体层与有源区的表面分离。

公开(公告)号：US07307336B2

公开(公告)日：2007-12-11

申请号：US10497827

申请日：2002-12-06

申请人： Karl-Ernst Ehwald ,  Alexander Fox ,  Dieter Knoll ,  Bernd Heinemann ,  Steffen Marschmayer ,  Katrin Blum

发明人： Karl-Ernst Ehwald ,  Alexander Fox ,  Dieter Knoll ,  Bernd Heinemann ,  Steffen Marschmayer ,  Katrin Blum

IPC分类号： H01L27/102

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： The invention concerns a bipolar transistor with an epitaxially grown base and a self-positioned emitter, whereby the base is formed from a first substantially monocrystalline epitaxial region (1) which is arranged in parallel relationship to the surface of the semiconductor substrate (2) and a second substantially polycrystalline and highly doped region (3) of the same conductivity type which is arranged in perpendicular relationship to the substrate surface and encloses the first region at all sides and that said second region, at least at one side but preferably at all four sides, is conductingly connected to a third, preferably highly doped or metallically conducting, high temperature-resistant polycrystalline layer (4) which is arranged in parallel relationship to the surface of the semiconductor substrate and forms or includes the outer base contact to a metallic conductor track system.

摘要翻译： 本发明涉及一种具有外延生长的基极和自定位发射极的双极晶体管，由此该基极由与半导体衬底（2）的表面平行关系设置的第一基本单晶外延区（1）形成，以及 相同导电类型的第二基本上多晶和高度掺杂的区域（3），其被布置成与衬底表面成垂直的关系，并且在所有侧面包围第一区域，并且所述第二区域至少在一侧，但优选地全部为四个 侧面与第三，优选高度掺杂或金属导电的耐高温多晶层（4）导电连接，该多晶层与半导体衬底的表面平行地布置，并形成或包括与金属导体 轨道系统

公开(公告)号：US20050006724A1

公开(公告)日：2005-01-13

申请号：US10497827

申请日：2002-12-06

申请人： Karl-Ernst Ehwald ,  Alexander Fox ,  Dieter Knoll ,  Bernd Heinemann ,  Steffen Marschmayer ,  Katrin Blum

发明人： Karl-Ernst Ehwald ,  Alexander Fox ,  Dieter Knoll ,  Bernd Heinemann ,  Steffen Marschmayer ,  Katrin Blum

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： The invention concerns a bipolar transistor with an epitaxially grown base and a self-positioned emitter, whereby the base is formed from a first substantially monocrystalline epitaxial region (1) which is arranged in parallel relationship to the surface of the semiconductor substrate (2) and a second substantially polycrystalline and highly doped region (3) of the same conductivity type which is arranged in perpendicular relationship to the substrate surface and encloses the first region at all sides and that said second region, at least at one side but preferably at all four sides, is conductingly connected to a third, preferably highly doped or metallically conducting, high temperature-resistant polycrystalline layer (4) which is arranged in parallel relationship to the surface of the semiconductor substrate and forms or includes the outer base contact to a metallic conductor track system.

摘要翻译： 本发明涉及一种具有外延生长的基极和自定位发射极的双极晶体管，由此该基极由与半导体衬底（2）的表面平行关系设置的第一基本单晶外延区（1）形成，以及 相同导电类型的第二基本上多晶和高度掺杂的区域（3），其被布置成与衬底表面成垂直的关系，并且在所有侧面包围第一区域，并且所述第二区域至少在一侧，但优选地全部为四个 侧面与第三，优选高度掺杂或金属导电的耐高温多晶层（4）导电连接，该多晶层与半导体衬底的表面平行地布置，并形成或包括与金属导体 轨道系统

公开(公告)号：US06740560B1

公开(公告)日：2004-05-25

申请号：US09857859

申请日：2001-09-17

申请人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll

发明人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The aim of the invention is to provide for a bipolar transistor and a method for producing the same. Said bipolar transistor should have minimal base-emitter capacities and very good high frequency characteristics. The static characteristics, especially the base current ideality and the low frequency noise, of a bipolar transistor with weakly doped cap layer (116) should not significantly deteriorate and process complexity should not increase. According to the invention, the problem is solved by inserting a special doping profile in a cap layer (116) (cap doping) which has been produced epitaxially. A minimal base emitter capacity and very good high frequency characteristics can be obtained by means of said doping profile. At the same time, the efficiency of the generation/recombination active boundary surface between the cap layer (116) and the isolator (117) in the polysilicon overlapping area in the relevant working area of the transistor is reduced and the base current ideality is improved. The section at the base side in the cap layer (116) has a preferred thickness of between 20 nm and 70 nm and is only doped weakly, preferably less than 5·1016 cm−3. Said section is crucial for the good high frequency characteristics.

摘要翻译： 本发明的目的是提供一种双极晶体管及其制造方法。 所述双极晶体管应具有最小的基极 - 发射极容量和非常好的高频特性。 具有弱掺杂覆盖层（116）的双极晶体管的静态特性，特别是基极电流理想和低频噪声不应显着劣化，并且处理复杂度不应增加。 根据本发明，通过在已经外延生产的盖层（116）（帽掺杂）中插入特殊的掺杂分布来解决问题。 通过所述掺杂分布可以获得最小的基极发射极容量和非常好的高频特性。 同时，晶体管的相关工作区域中的多晶硅重叠区域中的覆盖层（116）和隔离器（117）之间的生成/复合有源边界面的效率降低，并且提高了基极电流理想度 。 盖层（116）中的底侧的截面具有20nm至70nm之间的优选厚度，并且仅掺杂较弱，优选小于5.10cm -3。 所述部分对于良好的高频特性至关重要。