公开(公告)号：US20050121750A1

公开(公告)日：2005-06-09

申请号：US10728995

申请日：2003-12-05

申请人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

IPC分类号： H01L21/033 ,  H01L21/336 ,  H01L23/58

CPC分类号： H01L29/4983 ,  H01L21/0337 ,  H01L29/6653 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

摘要翻译： 一种制造微电子器件的方法，包括在衬底上形成图案化特征，并使用含氟等离子体源将图形化特征和衬底上的共形聚合物层沉积。 蚀刻聚合物层以暴露图案化特征和基底的一部分，由此在图案化特征的相对侧上形成聚合物间隔物。

公开(公告)号：US07202172B2

公开(公告)日：2007-04-10

申请号：US10728995

申请日：2003-12-05

申请人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yu-I Wang ,  Han-Jan Tao

IPC分类号： H01L21/311

CPC分类号： H01L29/4983 ,  H01L21/0337 ,  H01L29/6653 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

摘要翻译： 一种制造微电子器件的方法，包括在衬底上形成图案化特征，并使用含氟等离子体源将图形化特征和衬底上的共形聚合物层沉积。 蚀刻聚合物层以暴露图案化特征和基底的一部分，由此在图案化特征的相对侧上形成聚合物间隔物。

公开(公告)号：US20060148181A1

公开(公告)日：2006-07-06

申请号：US11026009

申请日：2004-12-31

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.

摘要翻译： 包括完全硅化栅电极的应变通道NMOS和PMOS器件对及其形成方法，该方法包括提供包含NMOS和PMOS器件区域的半导体衬底，PMOS器件区域包括包括多晶硅栅电极的各自的栅极结构; 在包括所述NMOS和PMOS器件区域中的至少一个的沟道区域的任一侧上形成凹陷区域; 用半导体硅合金回填凹陷区域，以在沟道区域上施加应变; 在栅极结构的任一侧上形成偏置间隔物; 将多晶硅栅电极减薄至硅化厚度，以允许通过硅化物厚度的全金属硅化物; 离子注入多晶硅栅电极以调节功函数; 并通过硅化物厚度形成金属硅化物以形成金属硅化物栅电极。

公开(公告)号：US07195969B2

公开(公告)日：2007-03-27

申请号：US11026009

申请日：2004-12-31

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.

摘要翻译： 包括完全硅化栅电极的应变通道NMOS和PMOS器件对及其形成方法，该方法包括提供包含NMOS和PMOS器件区域的半导体衬底，PMOS器件区域包括包括多晶硅栅电极的各自的栅极结构; 在包括所述NMOS和PMOS器件区域中的至少一个的沟道区域的任一侧上形成凹陷区域; 用半导体硅合金回填凹陷区域，以在沟道区域上施加应变; 在栅极结构的任一侧上形成偏置间隔物; 将多晶硅栅电极减薄至硅化厚度，以允许通过硅化物厚度的全金属硅化物; 离子注入多晶硅栅电极以调节功函数; 并通过硅化物厚度形成金属硅化物以形成金属硅化物栅电极。

公开(公告)号：US06828237B1

公开(公告)日：2004-12-07

申请号：US10662069

申请日：2003-09-11

申请人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21311

CPC分类号： H01L21/0338 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823437

摘要： A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.

摘要翻译： 用于在微电子产品内形成图案化目标层的等离子体蚀刻方法形成邻接形成在覆盖目标层上的图案化掩模层的蚀刻残余层。 在去除图案化的掩模层之后，蚀刻残余层被横向增加以形成横向增加的蚀刻残留层。 使用横向增加的蚀刻残留层作为用于从覆盖目标层形成图案化目标层的蚀刻掩模。 该方法对于在半导体产品中形成栅电极特别有用。

公开(公告)号：US20050081781A1

公开(公告)日：2005-04-21

申请号：US10688045

申请日：2003-10-17

申请人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/316 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31645 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513

摘要： A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.

摘要翻译： 描述了用于从衬底去除高k电介质层而不损坏衬底并且相对于栅极层具有高选择性的全干蚀刻方法。 蚀刻由BCl 3 3，碳氟化合物和惰性气体组成。 低RF偏置功率是优选的。 该方法也可以用于去除衬底和高k电介质层之间的界面层。 实现了每分钟55埃的HfO 2/2蚀刻速率，而不会在硅衬底中产生凹陷，并且对多晶硅的蚀刻选择性大于10:1。 该方法也提供更好的STI氧化物控制。 通过高k介电层的蚀刻可以在与蚀刻工艺相同的蚀刻室中进行以形成栅电极。