公开(公告)号：US06870379B1

公开(公告)日：2005-03-22

申请号：US10164739

申请日：2002-06-06

申请人： Brennan V. Davis ,  Victoria J. Bruce ,  Michael R. Bruce ,  Rosalinda M. Ring ,  David H. Eppes

发明人： Brennan V. Davis ,  Victoria J. Bruce ,  Michael R. Bruce ,  Rosalinda M. Ring ,  David H. Eppes

IPC分类号： G01R31/311 ,  G01R31/302 ,  G01R31/26

CPC分类号： G01R31/311

摘要： Analysis of a semiconductor die is enhanced by the stimulation the die and the detection of a response to the stimulation. According to an example embodiment of the present invention, a semiconductor die is analyzed using indirect stimulation of a portion of the die, and detecting a response therefrom. First, selected portion of circuitry within the die is stimulated. The stimulation of the selected portion induces a second portion of circuitry within the die to generate an external emission. The emission is detected and the die is analyzed therefrom. In one particular implementation, a response from the selected portion is inhibited from interfering with the detection of the emission from the second portion of circuitry.

摘要翻译： 通过刺激模具和检测对刺激的响应来增强半导体管芯的分析。 根据本发明的示例性实施例，使用间接刺激芯片的一部分并且从其检测响应来分析半导体管芯。 首先，刺激模具内的电路的选定部分。 所选部分的刺激引起管芯内的电路的第二部分以产生外部发射。 检测发射并从中分析模具。 在一个具体实现中，来自所选择的部分的响应被禁止干扰来自电路的第二部分的发射的检测。

公开(公告)号：US06635839B1

公开(公告)日：2003-10-21

申请号：US09838672

申请日：2001-04-19

申请人： Glen P. Gilfeather ,  Srikar V. Chunduri ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

发明人： Glen P. Gilfeather ,  Srikar V. Chunduri ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

IPC分类号： B07C500

CPC分类号： G01N21/9501 ,  G01R31/311

摘要： Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

摘要翻译： 使用适于扰动测试室中的管芯并检测从管芯到扰动的响应的系统来增强半导体管芯分析。 根据本发明的示例性实施例，半导体管芯分析系统包括测试室和适于与测试室对接的对接装置。 模具保持在对接装置中，并且当对接装置与腔室对接时，将模具放置在测试室的内部。 使用两个或更多个扰动装置扰乱管芯，并且控制器适于控制扰动。 数据采集​​装置响应于扰动从管芯接收数据，并且数据用于分析管芯。

公开(公告)号：US06844928B1

公开(公告)日：2005-01-18

申请号：US09838717

申请日：2001-04-19

申请人： Glen P. Gilfeather ,  Srikar V. Chunduri ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

发明人： Glen P. Gilfeather ,  Srikar V. Chunduri ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

IPC分类号： G01N21/95 ,  G01N21/00

CPC分类号： G01N21/9501

摘要： The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.

摘要翻译： 使用在光源和管芯之间引导光的方法和装置来增强基于光的半导体管芯分析的可操作性。 在本发明的一个示例实施例中，使用光纤电缆将光源引导到半导体分析装置中的管芯。 分析装置适于使用经由光纤电缆接收的光来分析模具。 该分析包括一种或多种基于光的应用，例如用光刺激所述裸片的选定部分并检测其中的响应。 以这种方式，可以在各种分析实现中将光导向模具，例如用于在测试室中分析模具。

公开(公告)号：US06700659B1

公开(公告)日：2004-03-02

申请号：US09838671

申请日：2001-04-19

申请人： Srikar V. Chunduri ,  Glen P. Gilfeather ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

发明人： Srikar V. Chunduri ,  Glen P. Gilfeather ,  Brennan V. Davis ,  David H. Eppes ,  Victoria Bruce ,  Michael Bruce ,  Rosalinda M. Ring ,  Daniel Stone

IPC分类号： G01N2188

CPC分类号： G01R31/311 ,  G01N21/9501

摘要： The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.

摘要翻译： 使用可以检测光源和管芯之间的光泄漏的方法和装置来增强基于光的半导体管芯分析的可操作性。 在本发明的一个示例性实施例中，使用例如光纤电缆将光源引导到半导体分析装置。 分析装置适于使用来自光源的光来分析模具。 光检测装置检测来自系统的光泄漏的状况，并产生表示漏光状况的信号。 所产生的信号然后可以用于控制半导体分析装置，例如通过响应于检测到的泄漏而停用光源，或者通过允许光源响应于不检测泄漏而起作用。

公开(公告)号：US06836132B1

公开(公告)日：2004-12-28

申请号：US10113604

申请日：2002-03-29

申请人： Michael R. Bruce ,  David H. Eppes ,  Rama R. Goruganthu

发明人： Michael R. Bruce ,  David H. Eppes ,  Rama R. Goruganthu

IPC分类号： G01R3128

CPC分类号： H01L22/20 ,  G01K7/015 ,  G01R31/303

摘要： A semiconductor device is analyzed and manufactured using a heat-exchange probe. According to an example embodiment of the present invention, a heat-exchange probe is controlled to exchange heat to a portion of a semiconductor device using sub-micron resolution. In one implementation, sub-micron resolution is achieved using a navigational arrangement, such as microscope, adapted to direct light to within about one micron of a target circuit portion on a plane of the device. In another implementation, a physical heat probe tip (e.g., a metal probe having about a one micron diameter probe tip) is navigated to a selected portion of the device using sub-micron navigational resolution. In each of these implementations, as well as others, the heat exchange is preponderantly confined to within about a one micron radius of a target portion of circuitry on lateral plane of the device. With this approach, heat exchange can be controlled to selectively stimulate circuitry within the device, which is particularly useful in high-density circuit implementations.

摘要翻译： 使用热交换探针分析和制造半导体器件。 根据本发明的示例性实施例，控制热交换探针以使用亚微米分辨率将热量交换到半导体器件的一部分。 在一个实施方案中，使用诸如显微镜的导航装置来实现亚微米分辨率，其适于将光引导到设备平面上的目标电路部分的约一微米内。 在另一个实施方案中，使用亚微米导航分辨率将物理热探针尖端（例如，具有约一微米直径的探针尖端的金属探针）导航到装置的选定部分。 在这些实施方案的每一个以及其它实施方案中，热交换主要被限制在装置的横向平面上的电路的目标部分的约一微米半径内。 利用这种方法，可以控制热交换以选择性地刺激装置内的电路，这在高密度电路实现中特别有用。

公开(公告)号：US06956385B1

公开(公告)日：2005-10-18

申请号：US09915883

申请日：2001-07-26

申请人： Michael R. Bruce ,  David H. Eppes

发明人： Michael R. Bruce ,  David H. Eppes

IPC分类号： G01K11/00 ,  G01R31/302 ,  G01R31/311 ,  H01L21/66

CPC分类号： G01R31/311 ,  H01L22/24

摘要： Defect analysis of an integrated circuit die having a back side opposite circuitry at a circuit side and a liquid crystal liquid is enhanced using near infrared (nIR) laser light. According to an example embodiment of the present invention, nIR laser light is directed to an integrated circuit die having a liquid crystal layer formed over the die. When the die includes a defect that generates heat, the heat generated in the die as a result of the nIR laser light adds to the heat in the die generated as a result of the defect and causes a portion of the liquid crystal layer to change phase near the defect. The phase change is detected and used to identify a portion of the die having a defect.

摘要翻译： 使用近红外（nIR）激光增强了具有电路侧背面相对电路的集成电路芯片和液晶液体的缺陷分析。 根据本发明的示例性实施例，nIR激光被引导到具有在模具上形成的液晶层的集成电路管芯。 当模具包含产生热量的缺陷时，作为nIR激光的结果，在管芯中产生的热量增加了由于缺陷而产生的管芯中的热量，并使一部分液晶层改变相位 靠近缺陷。 检测相变并用于识别具有缺陷的模具的一部分。

公开(公告)号：US09318464B2

公开(公告)日：2016-04-19

申请号：US13899080

申请日：2013-05-21

申请人： David H. Eppes

发明人： David H. Eppes

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/00 ,  H01L25/00 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L24/81 ,  H01L22/14 ,  H01L22/20 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

摘要翻译： 公开了将半导体芯片安装在基板上的各种方法。 一方面，提供一种制造方法，其包括将第一多个焊料互连结构耦合到第一半导体芯片。 第一焊料互连结构具有第一熔点。 可以测试第一个半导体芯片。 如果第一半导体芯片通过测试，则使用具有低于第一熔点的第二熔点的第二多个焊料互连结构将第二半导体芯片耦合到第一半导体芯片。

公开(公告)号：US20140346664A1

公开(公告)日：2014-11-27

申请号：US13899080

申请日：2013-05-21

申请人： David H. Eppes

发明人： David H. Eppes

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L22/14 ,  H01L22/20 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

摘要翻译： 公开了将半导体芯片安装在基板上的各种方法。 一方面，提供一种制造方法，其包括将第一多个焊料互连结构耦合到第一半导体芯片。 第一焊料互连结构具有第一熔点。 可以测试第一个半导体芯片。 如果第一半导体芯片通过测试，则使用具有低于第一熔点的第二熔点的第二多个焊料互连结构将第二半导体芯片耦合到第一半导体芯片。

公开(公告)号：US07091621B1

公开(公告)日：2006-08-15

申请号：US10768179

申请日：2004-02-02

申请人： David H. Eppes

发明人： David H. Eppes

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L22/34 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure prevents crack propagation to the active die circuitry of a main die area during sawing around the outer periphery of the main die area. Stress relief elements, such as dummy vias, are provided in the scribe line area between the saw lane and the main die area. The dummy vias prevent cracks induced by the sawing process from propagating to the main die area.

摘要翻译： 一种方法和结构防止在围绕主模具区域的外周边锯切期间的裂纹传播到主模具区域的有源管芯电路。 应力消除元件，例如虚拟通孔，设置在锯道和主模区之间的划线区域。 虚拟通孔防止锯切过程引起的裂纹传播到主模具区域。