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1.发明授权Semiconductor structure with reduced gate doping and methods for forming thereof 有权减少栅极掺杂的半导体结构及其形成方法公开(公告)号：US07488635B2
公开(公告)日：2009-02-10
申请号：US11260849
申请日：2005-10-26
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.
摘要翻译： 半导体结构包括具有存储区域和逻辑区域的衬底。 第一p型器件形成在存储器区域中，并且第二p型器件形成在逻辑区域中。 第一p型器件的半导体栅极的至少一部分具有比第二p型器件的半导体栅极的至少一部分更低的p型掺杂剂浓度。 第一和第二p型器件的半导体栅极各自具有非零p型掺杂剂浓度。
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公开(公告)号：US20080099808A1
公开(公告)日：2008-05-01
申请号：US11554851
申请日：2006-10-31
IPC分类号： H01L29/94
CPC分类号： H01L27/10802 , G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/10844 , H01L29/7839 , H01L29/7841
摘要： A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
摘要翻译： 单晶体管动态随机存取存储器（DRAM）单元包括晶体管，其具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的主体区域以及在主体上的栅极 地区。 第一源极/漏极区域包括与主体区域的肖特基二极管结，并且第二源极/漏极区域包括与身体区域的n-p二极管结。
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公开(公告)号：US08283244B2
公开(公告)日：2012-10-09
申请号：US12558284
申请日：2009-09-11
IPC分类号： H01L21/44
CPC分类号： H01L27/10802 , G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/10844 , H01L29/7839 , H01L29/7841
摘要： A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
摘要翻译： 单晶体管动态随机存取存储器（DRAM）单元包括晶体管，其具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的主体区域以及在主体上的栅极 地区。 第一源极/漏极区域包括与主体区域的肖特基二极管结，并且第二源极/漏极区域包括与身体区域的n-p二极管结。
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公开(公告)号：US07608898B2
公开(公告)日：2009-10-27
申请号：US11554851
申请日：2006-10-31
IPC分类号： H01L29/78 , H01L21/8242
CPC分类号： H01L27/10802 , G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/10844 , H01L29/7839 , H01L29/7841
摘要： A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
摘要翻译： 单晶体管动态随机存取存储器（DRAM）单元包括晶体管，其具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的主体区域以及在主体上的栅极 地区。 第一源极/漏极区域包括与主体区域的肖特基二极管结，并且第二源极/漏极区域包括与身体区域的n-p二极管结。
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5.发明授权Electronic device including a static-random-access memory cell and a process of forming the electronic device 有权包括静态随机存取存储单元的电子设备和形成电子设备的过程公开(公告)号：US07414877B2
公开(公告)日：2008-08-19
申请号：US11337355
申请日：2006-01-23
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/845 , H01L27/1211 , H01L29/045
摘要： An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.
摘要翻译： 电子设备可以包括静态随机存取存储器单元。 静态随机存取存储器单元可以包括第一类型的第一晶体管和第二类型的第二晶体管。 第一晶体管可以具有沿着第一线延伸的第一沟道长度，并且第二晶体管可以具有沿着第二线延伸的第二沟道长度。 第一行和第二行可以以不同于22.5°的整数倍的值相交。 在特定实施例中，第一晶体管可以包括上拉晶体管，并且第二晶体管可以包括通过栅极或下拉晶体管。 可以使用一种方法来形成包括栅电极部分的半导体鳍片和导电构件，以实现包括第一和第二晶体管的电子器件。
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公开(公告)号：US07799644B2
公开(公告)日：2010-09-21
申请号：US11460782
申请日：2006-07-28
IPC分类号： H01L21/8234 , H01L21/44
CPC分类号： H01L21/823835 , H01L21/823814 , H01L27/0922
摘要： A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.
摘要翻译： 具有比漏极更高电阻的源极的晶体管作为存储电路中的上拉器件是最佳的。 晶体管具有源极区域，源极源极具有源极电阻。 来源地区没有水淹。 控制电极区域与源极区域相邻，用于控制晶体管的导电。 漏极区域与控制电极区域相邻并与源极区域相对。 漏极区域具有被浸没并具有漏极电阻的漏极注入。 源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。
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公开(公告)号：US20080026529A1
公开(公告)日：2008-01-31
申请号：US11460782
申请日：2006-07-28
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823814 , H01L27/0922
摘要： A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.
摘要翻译： 具有比漏极更高电阻的源极的晶体管作为存储电路中的上拉器件是最佳的。 晶体管具有源极区域，源极源极具有源极电阻。 来源地区没有水淹。 控制电极区域与源极区域相邻，用于控制晶体管的导电。 漏极区域与控制电极区域相邻并与源极区域相对。 漏极区域具有被浸没并具有漏极电阻的漏极注入。 源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。
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8.发明授权Method of making a split gate non-volatile memory (NVM) cell and a logic transistor 有权分离门非易失性存储器（NVM）单元和逻辑晶体管的制造方法公开(公告)号：US09257445B2
公开(公告)日：2016-02-09
申请号：US14291224
申请日：2014-05-30
IPC分类号： H01L29/49 , H01L27/115 , H01L21/285 , H01L29/423 , H01L21/28 , H01L29/78 , H01L29/66
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L21/28525 , H01L27/11534 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/4916 , H01L29/517 , H01L29/6656 , H01L29/66825 , H01L29/66833 , H01L29/7843 , H01L29/7881 , H01L29/792
摘要： Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.
摘要翻译： 用于制造半导体结构的半导体结构和方法包括NVM区域中的分裂门非易失性存储器（NVM）单元。 电荷存储层，第一导电层和覆盖层形成在衬底上，其被图案化以在衬底的NVM区域中形成控制栅极堆叠。 在基板上形成高k电介质层，金属层和第二导电层。 图案化第二导电层和金属层，以在控制栅极堆叠的第一侧上并与之相邻地形成第二导电层和金属层的剩余部分。 去除第二导电层的剩余部分以形成包括金属层的剩余部分的选择栅叠层。 在衬底上形成应力层。
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公开(公告)号：US08962410B2
公开(公告)日：2015-02-24
申请号：US13282210
申请日：2011-10-26
IPC分类号： H01L21/337 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823493 , H01L21/823412 , H01L21/823807 , H01L21/823892
摘要： A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.
摘要翻译： 第一晶体管和第二晶体管形成有不同的阈值电压。 第一栅极形成在用于第一晶体管的衬底的第一区域上，并且在第二区域上形成用于第二晶体管的第二栅极。 第一个区域被屏蔽。 通过在掩蔽第一区域的同时通过第二栅极注入来调节第二晶体管的阈值电压。 电流电极区域形成在第二栅极的相对侧上的第一栅极和电流电极区域的相对侧上。
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10.发明授权Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor 有权具有具有不同密度的纳米晶体的不同非易失性存储器的半导体器件及其方法公开(公告)号：US08679912B2
公开(公告)日：2014-03-25
申请号：US13362697
申请日：2012-01-31
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。
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