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22 条记录 (耗时 0.042 秒)

    Modular process transmitter having a scalable EMI/RFI filtering architecture
    6.
    发明授权
    Modular process transmitter having a scalable EMI/RFI filtering architecture 有权
    具有可扩展的EMI / RFI滤波架构的模块化过程变送器

    公开(公告)号：US06593857B1

    公开(公告)日：2003-07-15

    申请号：US09638181

    申请日：2000-07-31

    申请人： Weston Roper ,  Todd M. Berge ,  David G. Tyson ,  Brian L. Westfield ,  Richard L. Nelson

    发明人： Weston Roper ,  Todd M. Berge ,  David G. Tyson ,  Brian L. Westfield ,  Richard L. Nelson

    IPC分类号： G08C1900

    CPC分类号： G01D1/00 ,  G01L13/026 ,  G01L19/0084 ,  G01L19/0663 ,  G01L19/069 ,  G01L19/083 ,  H01R13/527 ,  H01R29/00 ,  Y10S439/912 ,  Y10T29/49002

    摘要： A modular process transmitter having a scalable EMI/RFI filtering architecture includes a unitized sensor module and a transmitter module. The unitized sensor module is adapted to operate as a stand-alone process transmitter. The transmitter module can couple to the unitized sensor module to expand the capabilities of the unitized sensor module. The unitized sensor module includes a sensor housing, a sensor circuit and a removable sensor EMI/RFI filtering circuit. The sensor circuit provides a sensor output in accordance with either a local format or a first communication protocol. The sensor EMI/RFI filtering circuit filters noise in accordance with the first communication protocol. The transmitter module includes a transmitter module housing, a communications circuit, and a transmitter module EMI/RFI filtering circuit. The communications circuit is adapted to receive the sensor output from the sensor circuit in the local format and generate a scalable output in accordance with a second communication protocol. The transmitter module EMI/RFI filtering circuit is adapted to replace the sensor EMI/RFI filtering circuit and filter noise in accordance with the second communication protocol.

    摘要翻译： 具有可扩展EMI / RFI滤波架构的模块化过程变送器包括单元化传感器模块和发射器模块。 单元化传感器模块适用于独立的过程变送器。 发射机模块可以耦合到单元化的传感器模块，以扩大组合式传感器模块的功能。 组合式传感器模块包括传感器外壳，传感器电路和可移动传感器EMI / RFI滤波电路。 传感器电路根据本地格式或第一通信协议提供传感器输出。 传感器EMI / RFI滤波电路根据第一个通信协议对噪声进行滤波。 发射机模块包括发射机模块外壳，通信电路和发射机模块EMI / RFI滤波电路。 通信电路适于以本地格式从传感器电路接收传感器输出，并根据第二通信协议生成可缩放的输出。 发射机模块EMI / RFI滤波电路适用于根据第二通信协议来替代传感器EMI / RFI滤波电路和滤波器噪声。

    Process control transmitter having an externally accessible DC circuit common
    7.
    发明授权
    Process control transmitter having an externally accessible DC circuit common 有权
    具有外部可访问的DC电路的过程控制变送器是公共的

    公开(公告)号：US06504489B1

    公开(公告)日：2003-01-07

    申请号：US09571111

    申请日：2000-05-15

    申请人： Brian L. Westfield ,  Weston Roper ,  Richard L. Nelson

    发明人： Brian L. Westfield ,  Weston Roper ,  Richard L. Nelson

    IPC分类号： G08C1900

    CPC分类号： G08C19/02

    摘要： Disclosed is a process control transmitter having an externally accessible DC circuit common that eliminates the need to perform level shifting of signals communicated between the transmitter and external processing electronics. The process control transmitter includes first, second and third terminals which feedthrough a housing. Circuitry contained in the housing is coupled to the first, second and third terminals and is adapted to communicate information to external processing electronics through the second and third terminals using a digital signal that is regulated relative to a DC common that is coupled to the second terminal. External processing electronics can couple to the second and third terminals and interpret the digital signal without having to perform level-shifting adjustments.

    摘要翻译： 公开了一种具有外部可访问的DC电路的过程控制发送器，其不需要执行在发射器和外部处理电子器件之间传送的信号的电平移位。 过程控制变送器包括穿过壳体的第一，第二和第三端子。 包含在壳体中的电路耦合到第一，第二和第三终端，并且适于使用相对于耦合到第二终端的DC公共端调节的数字信号通过第二和第三终端将信息传送到外部处理电子设备 。 外部处理电子器件可以耦合到第二和第三端子并且解释数字信号，而不必进行电平移位调整。

    RAM cell with soft error protection using ferroelectric material
    8.
    发明申请
    RAM cell with soft error protection using ferroelectric material 审中-公开
    使用铁电材料的具有软错误保护的RAM单元

    公开(公告)号：US20070103961A1

    公开(公告)日：2007-05-10

    申请号：US11268006

    申请日：2005-11-07

    申请人： Weston Roper ,  Cheisan Yue

    发明人： Weston Roper ,  Cheisan Yue

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/4125

    摘要： A static random access memory (SRAM) cell with single event and soft error protection using ferroelectric material is presented. The SRAM cell comprises two inverters in a mutual feedback loop, with the output of each of the inverters coupled to the input of the other. A ferroelectric capacitor is coupled to the output of one of the inverters in order to induce an RC delay and provide single event upset (SEU), single event effect (SEE), single event transient (SET), and soft error protection. In addition, a method is presented where ferroelectric capacitor of the system is fabricated after the underlayers of the SRAM cell have been implemented in order to avoid substantial changes to standard underlayer processing.

    摘要翻译： 介绍了使用铁电材料的单事件和软错误保护的静态随机存取存储器（SRAM）单元。 SRAM单元包括互反馈环路中的两个反相器，每个反相器的输出耦合到另一个的输入端。 铁电电容器耦合到一个逆变器的输出端，以引起RC延迟，并提供单次事件不平衡（SEU），单事件效应（SEE），单事件瞬态（SET）和软错误保护。 另外，在SRAM单元的底层已被实现以避免对标准底层处理的实质性改变之后，制造了系统的铁电电容器的方法。

    Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line
    9.
    发明授权
    Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line 有权
    用于补偿数字延迟线的时间延迟的过程，电压和温度变化的装置和方法

    公开(公告)号：US08390352B2

    公开(公告)日：2013-03-05

    申请号：US12418981

    申请日：2009-04-06

    申请人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

    发明人： James Seefeldt ,  Xiaoxin Feng ,  Weston Roper

    IPC分类号： H03L7/00

    CPC分类号： G11C29/022 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K2005/00097 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

    摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

    摘要翻译： 提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。 补偿电路包括两个延迟线，每个延迟线提供延迟输出。 两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。 延迟线的数量可能在两个延迟线之间不同。 延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。 延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM， 处理器或其他时钟电路。

    Circuit for aligning clock to parallel data
    10.
    发明授权
    Circuit for aligning clock to parallel data 有权
    将时钟对准并行数据的电路

    公开(公告)号：US08355478B1

    公开(公告)日：2013-01-15

    申请号：US12475414

    申请日：2009-05-29

    申请人： James Douglas Seefeldt ,  Weston Roper ,  James Hansen

    发明人： James Douglas Seefeldt ,  Weston Roper ,  James Hansen

    IPC分类号： H04L7/033

    CPC分类号： H03L7/08

    摘要： Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.

    摘要翻译： 描述了将时钟信号对准并行数据的方法和系统。 根据一个实施例，时钟移位电路相对于输入数据信号移动输入时钟信号，并且数据时钟电路使用移位时钟信号重新锁定输入数据信号。 时钟转换电路可以包括与多个D触发器（DFF）串联连接的锁相环（PLL）。 分数组合逻辑可以设置在该系列中的DFF之间。 数据时钟电路可以包括一个DFF以重新锁定每个输入数据位，一对DFF以重新锁定每个输入数据位，或其他电路，例如真实补码块，以用作混频器的本地振荡器。 可以产生多个移位时钟信号，例如相对于输入时钟信号偏移60,90,120,180,240和270度的移位时钟信号。