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1.发明申请RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION 有权接收通道阵列晶体管（RCAT）结构和形成方法公开(公告)号：US20110121385A1
公开(公告)日：2011-05-26
申请号：US13017309
申请日：2011-01-31
IPC分类号： H01L27/092
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.
摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。
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公开(公告)号：US08148772B2
公开(公告)日：2012-04-03
申请号：US13017309
申请日：2011-01-31
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.
摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。
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3.发明申请RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION 有权接收通道阵列晶体管（RCAT）结构和形成方法公开(公告)号：US20100264494A1
公开(公告)日：2010-10-21
申请号：US12826954
申请日：2010-06-30
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.
摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。
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4.发明申请RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION 有权接收通道阵列晶体管（RCAT）结构和形成方法公开(公告)号：US20090294839A1
公开(公告)日：2009-12-03
申请号：US12130581
申请日：2008-05-30
IPC分类号： H01L29/76 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.
摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。
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公开(公告)号：US20150091067A1
公开(公告)日：2015-04-02
申请号：US14040574
申请日：2013-09-27
申请人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
发明人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
CPC分类号： H01L27/2436 , H01L29/66477 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L2029/7858
摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
摘要翻译： 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。
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6.发明授权Trigate static random-access memory with independent source and drain engineering, and devices made therefrom 有权调整静态随机存取存储器，具有独立的源和漏极工程，以及由此制造的器件公开(公告)号：US08674448B2
公开(公告)日：2014-03-18
申请号：US13563432
申请日：2012-07-31
IPC分类号： H01L21/70
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/845 , H01L27/11 , H01L27/1211
摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
摘要翻译： 静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分 地区。 静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。 实现静态随机存取存储器电路的过程包括源极和漏极外延。
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公开(公告)号：US07898023B2
公开(公告)日：2011-03-01
申请号：US12826954
申请日：2010-06-30
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.
摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。
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8.发明申请FIN FIELD EFFECT TRANSISTOR STRUCTURES HAVING TWO DIELECTRIC THICKNESSES 审中-公开具有两个电介质厚度的FIN场效应晶体管结构公开(公告)号：US20090206405A1
公开(公告)日：2009-08-20
申请号：US12032594
申请日：2008-02-15
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/517 , H01L29/66795 , H01L29/7841 , H01L29/785
摘要： Fin field-effect-transistor (finFET) structures having two dielectric thicknesses are generally described. In one example, an apparatus includes a semiconductor substrate, a semiconductor fin coupled with the semiconductor substrate, the semiconductor fin having at least a first surface, a second surface, and a third surface, the third surface being substantially parallel to the first surface and substantially perpendicular to the second surface, a spacer dielectric coupled to the second surface of the semiconductor fin, a back gate dielectric having a back gate dielectric thickness coupled to the first surface of the semiconductor fin, and a front gate dielectric having a front gate dielectric thickness coupled to the third surface of the semiconductor fin wherein the back gate dielectric thickness is greater than the front gate dielectric thickness
摘要翻译： 通常描述具有两个介电厚度的鳍场效应晶体管（finFET）结构。 在一个示例中，装置包括半导体衬底，与半导体衬底耦合的半导体鳍片，半导体鳍片具有至少第一表面，第二表面和第三表面，第三表面基本上平行于第一表面， 基本上垂直于第二表面的隔离电介质，耦合到半导体鳍片的第二表面的间隔电介质，具有耦合到半导体鳍片的第一表面的背栅电介质厚度的背栅电介质和具有前栅极电介质 耦合到半导体鳍片的第三表面的厚度，其中背栅电介质厚度大于前栅极电介质厚度
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9.发明申请INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS 审中-公开独立门电极增加多栅极晶体管的读稳定性公开(公告)号：US20090166743A1
公开(公告)日：2009-07-02
申请号：US11964633
申请日：2007-12-26
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/785
摘要： Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.
摘要翻译： 通常描述用于多栅极晶体管的独立栅电极。 在一个示例中，装置包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）栅极叠层，所述一个或多个PD栅极堆叠包括PD栅极电极和一个或多个多栅极 所述PG栅极堆叠与所述半导体鳍片耦合，所述一个或多个PG栅极堆叠包括PG栅极电极，所述PG栅电极具有比所述PD栅电极更大的阈值电压。
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10.发明授权公开(公告)号：US10516109B2
公开(公告)日：2019-12-24
申请号：US15529907
申请日：2014-12-24
申请人： Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
发明人： Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L45/00
摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
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