公开(公告)号：US08674448B2

公开(公告)日：2014-03-18

申请号：US13563432

申请日：2012-07-31

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian S. Doyle ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L21/70

CPC分类号： H01L27/1104 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211

摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.

摘要翻译： 静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分 地区。 静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。 实现静态随机存取存储器电路的过程包括源极和漏极外延。

公开(公告)号：US08785907B2

公开(公告)日：2014-07-22

申请号：US13722746

申请日：2012-12-20

申请人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van H. Le ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Sanaz K. Gardner ,  Sansaptak Dasgupta ,  Willy Rachmady ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Gilbert Dewey ,  Marc C. French ,  Jessica Kachian ,  Satyarth Suri ,  Robert S. Chau

发明人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van H. Le ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Sanaz K. Gardner ,  Sansaptak Dasgupta ,  Willy Rachmady ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Gilbert Dewey ,  Marc C. French ,  Jessica Kachian ,  Satyarth Suri ,  Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/76232

摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

摘要翻译： 实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。 一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。 实施例包括使用多个生长温度在沟槽内形成的EPI层。 当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。 缺陷屏障之上和沟槽内的EPI层相对无缺陷。 一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。 一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。 本文描述了其它实施例。

公开(公告)号：US20140103397A1

公开(公告)日：2014-04-17

申请号：US14141648

申请日：2013-12-27

申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20140054548A1

公开(公告)日：2014-02-27

申请号：US14069880

申请日：2013-11-01

申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

IPC分类号： H01L29/775 ,  H01L21/76 ,  H01L29/66

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20140008700A1

公开(公告)日：2014-01-09

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

摘要翻译： 描述具有底层扩散阻挡层的锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的栅极电极堆叠。 锗基活性层设置在基板上方，栅电极堆叠下方。 扩散阻挡层设置在基底上方，在锗活性层下方。 接点泄漏抑制层设置在基底上方，在扩散阻挡层下方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的结泄漏抑制层上方。

公开(公告)号：US20100155848A1

公开(公告)日：2010-06-24

申请号：US12317536

申请日：2008-12-24

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian Doyle ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian Doyle ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L27/1104 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211

摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.

摘要翻译： 静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分 地区。 静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。 实现静态随机存取存储器电路的过程包括源极和漏极外延。

公开(公告)号：US08987794B2

公开(公告)日：2015-03-24

申请号：US13997118

申请日：2011-12-23

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

摘要翻译： 描述了非平面栅极全面器件及其制造方法。 在一个实施例中，该器件包括具有第一晶格常数的顶表面的衬底。 嵌入的epi源极和漏极区域形成在衬底的顶表面上。 嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。 具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。 在一个实施例中，第二晶格常数和第三晶格常数不同于第一晶格常数。 通道纳米线包括最底部的沟道纳米线，并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。 在每个通道纳米线上形成栅极电介质层。 在栅极电介质层上形成栅电极并围绕每个沟道纳米线。

公开(公告)号：US20140225065A1

公开(公告)日：2014-08-14

申请号：US13997118

申请日：2011-12-23

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

摘要翻译： 描述了非平面栅极全面器件及其制造方法。 在一个实施例中，该器件包括具有第一晶格常数的顶表面的衬底。 嵌入的epi源极和漏极区域形成在衬底的顶表面上。 嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。 具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。 在一个实施例中，第二晶格常数和第三晶格常数不同于第一晶格常数。 通道纳米线包括最底部的沟道纳米线，并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。 在每个通道纳米线上形成栅极电介质层。 在栅极电介质层上形成栅电极并围绕每个沟道纳米线。

公开(公告)号：US08716751B2

公开(公告)日：2014-05-06

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L21/02

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

摘要翻译： 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US08592803B2

公开(公告)日：2013-11-26

申请号：US13442098

申请日：2012-04-09

申请人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/06 ,  H01L29/778

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.