公开(公告)号：US10516109B2

公开(公告)日：2019-12-24

申请号：US15529907

申请日：2014-12-24

申请人： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L45/00

摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

公开(公告)号：US10355205B2

公开(公告)日：2019-07-16

申请号：US15528674

申请日：2014-12-18

申请人： Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

发明人： Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L29/08 ,  H01L45/00

摘要： Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.

公开(公告)号：US20180226509A1

公开(公告)日：2018-08-09

申请号：US15747925

申请日：2015-07-31

申请人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/786 ,  H01L27/07 ,  H01L27/12 ,  H01L29/49 ,  H01L29/02

CPC分类号： H01L29/7869 ,  H01L27/0705 ,  H01L27/1225 ,  H01L27/2436 ,  H01L29/02 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78642 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：US08936976B2

公开(公告)日：2015-01-20

申请号：US12646711

申请日：2009-12-23

申请人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

发明人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L21/338 ,  H01L29/778 ,  H01L21/225 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

摘要翻译： 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US20110147798A1

公开(公告)日：2011-06-23

申请号：US12646711

申请日：2009-12-23

申请人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

发明人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

摘要翻译： 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US09443936B2

公开(公告)日：2016-09-13

申请号：US13870184

申请日：2013-04-25

申请人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L29/15 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/80 ,  H01L29/165 ,  H01L29/51

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US08258498B2

公开(公告)日：2012-09-04

申请号：US13017862

申请日：2011-01-31

申请人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L31/0328 ,  H01L31/109

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US07947971B2

公开(公告)日：2011-05-24

申请号：US12756989

申请日：2010-04-08

申请人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L31/0328 ,  H01L31/109

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US08501508B2

公开(公告)日：2013-08-06

申请号：US13479121

申请日：2012-05-23

申请人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L21/00

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20100193771A1

公开(公告)日：2010-08-05

申请号：US12756989

申请日：2010-04-08

申请人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

发明人： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC分类号： H01L29/772

CPC分类号： H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

摘要翻译： 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。