公开(公告)号：US20150137340A1

公开(公告)日：2015-05-21

申请号：US14540678

申请日：2014-11-13

Applicant: Broadcom Corporation

Inventor： Mark BUER ,  Matthew KAUFMANN

IPC: H01L23/00 ,  H01L23/04

CPC classification number: H01L23/573 ,  G06F21/87 ,  G06F2221/2143 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/576 ,  H01L24/06 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/30105 ,  Y10S257/922 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A secure integrated circuit package is provided. The secure integrated circuit package includes a first substrate having an upper surface and a lower surface. A first plurality of solder balls are arranged in a pattern on the lower surface of the first substrate. A die is coupled to the upper surface of the first substrate. A second plurality of solder balls is coupled to the upper surface of the substrate and arranged in a ring surrounding the die. A mesh substrate including a mesh protection grid is coupled to the second plurality of solder balls.

Abstract translation: 提供了一个安全的集成电路封装。 安全集成电路封装包括具有上表面和下表面的第一基板。 第一多个焊球以图案布置在第一基板的下表面上。 模具耦合到第一基板的上表面。 第二多个焊球联接到基板的上表面并且布置在围绕模具的环中。 包括网格保护网格的网格基板耦合到第二多个焊球。

公开(公告)号：US20140217573A1

公开(公告)日：2014-08-07

申请号：US14247222

申请日：2014-04-07

Applicant: Broadcom Corporation

Inventor： Mengzhi PANG ,  Ken Zhonghua WU ,  Matthew KAUFMANN

IPC: H01L23/34 ,  H01L23/12 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/34 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

Abstract translation: 公开了一种低成本和高性能倒装芯片封装。 通过使用衬底面板级工艺组装封装，避免了衬底的单独制造，从而能够使用无芯衬底。 无芯衬底可以包括具有导电迹线和通孔的层叠电介质膜的多层堆叠层。 结果，电连接路径可以直接从管芯接触焊盘提供到封装接触焊盘，而不需要使用常规的焊料凸块，因此容纳具有小特征尺寸的非常高密度的半导体管芯。 与具有焊料凸起的半导体管芯的常规制造的基板相比，所公开的倒装芯片封装提供了更低的成本，更高的电性能和改善的散热。