公开(公告)号：US20070152746A1

公开(公告)日：2007-07-05

申请号：US11323310

申请日：2005-12-30

申请人： Bryan Casper ,  Timothy Hollis ,  James Jaussi ,  Stephen Mooney ,  Frank O'Mahony ,  Mozhgan Mansuri

发明人： Bryan Casper ,  Timothy Hollis ,  James Jaussi ,  Stephen Mooney ,  Frank O'Mahony ,  Mozhgan Mansuri

IPC分类号： H03K5/00

CPC分类号： H03K5/1565 ,  H03H11/1291 ,  H03K5/01 ,  H03K5/1252 ,  H04L7/027

摘要： A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

摘要翻译： 一种可调谐带通滤波器，用于响应于输入差分时钟信号提供经滤波的差分时钟信号，其中实施例包括由可调谐负载加载的晶体管对，以及用于调谐可调负载的反馈电路。 在一些实施例中，反馈电路调谐负载以最大化小信号差分增益。 在其他实施例中，反馈电路调整负载以最小化指示经滤波的差分时钟信号中的抖动的度量。 描述和要求保护其他实施例。

公开(公告)号：US20070153445A1

公开(公告)日：2007-07-05

申请号：US11323370

申请日：2005-12-29

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen Mooney

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen Mooney

IPC分类号： H02B1/00

CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

公开(公告)号：US08571513B2

公开(公告)日：2013-10-29

申请号：US13540500

申请日：2012-07-02

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

IPC分类号： H04B1/28

CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

公开(公告)号：US20070115048A1

公开(公告)日：2007-05-24

申请号：US11268911

申请日：2005-11-07

申请人： Mozhgan Mansuri ,  Frank O'Mahony ,  Bryan Casper ,  James Jaussi

发明人： Mozhgan Mansuri ,  Frank O'Mahony ,  Bryan Casper ,  James Jaussi

IPC分类号： H03F1/02

CPC分类号： H03F3/45197 ,  H03F3/45744

摘要： In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.

摘要翻译： 在一些实施例中，提供了在其输出处具有可控地可变偏移的均衡器电路。

公开(公告)号：US20120281323A1

公开(公告)日：2012-11-08

申请号：US13540500

申请日：2012-07-02

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

IPC分类号： H02H9/04

CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

公开(公告)号：US08213894B2

公开(公告)日：2012-07-03

申请号：US11323370

申请日：2005-12-29

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

IPC分类号： H04B1/28

CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

公开(公告)号：US20070146011A1

公开(公告)日：2007-06-28

申请号：US11321371

申请日：2005-12-28

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Moonkyun Maeng

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Moonkyun Maeng

IPC分类号： H03K19/00

CPC分类号： H03K5/156 ,  G06F1/04

摘要： Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.

摘要翻译： 这里公开了用于控制时钟信号中的占空比的占空比调整电路。 在一些实施例中，提供了包括时钟驱动器的电路，以通过时钟路径驱动差分时钟信号。 反馈电路（i）耦合到时钟路径以监视时钟信号中的偏移，以及（ii）到时钟驱动器，以基于所监视的时钟信号偏移对时钟驱动器偏移进行数字控制。 本文公开了其它实施例。

公开(公告)号：US20050286623A1

公开(公告)日：2005-12-29

申请号：US10879948

申请日：2004-06-28

申请人： James Jaussi ,  Bryan Casper ,  Ganesh Balamurugan ,  Stephen Mooney

发明人： James Jaussi ,  Bryan Casper ,  Ganesh Balamurugan ,  Stephen Mooney

IPC分类号： H03H15/00 ,  H03H21/00 ,  H03K5/159 ,  H04L25/03

CPC分类号： H03H15/00 ,  H03H21/0001 ,  H03H2015/007 ,  H04L25/03038 ,  H04L2025/03726

摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.

摘要翻译： 在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是 第二个二进制值。 每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。 使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。 在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。 在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。 本发明的实施例具有对信道均衡的应用。

公开(公告)号：US20050134369A1

公开(公告)日：2005-06-23

申请号：US10743349

申请日：2003-12-23

申请人： Bryan Casper ,  Aaron Martin ,  James Jaussi ,  Stephen Mooney ,  Ganesh Balamurugan

发明人： Bryan Casper ,  Aaron Martin ,  James Jaussi ,  Stephen Mooney ,  Ganesh Balamurugan

IPC分类号： H03F1/02

CPC分类号： H03K5/19

摘要： An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.

摘要翻译： 提供一种集成电路，其包括从第一信道接收第一信号的第一端口和耦合到第一端口的第一设备，以修改从第一信道接收的第一信号的信道响应。 波形捕获装置可以耦合到第一装置以捕获由第一装置修改的信号的波形。

公开(公告)号：US20050053125A1

公开(公告)日：2005-03-10

申请号：US10660228

申请日：2003-09-10

申请人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

发明人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

IPC分类号： H03H21/00 ,  H04L25/03 ,  H03K5/159

CPC分类号： H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中在训练序列期间通过执行更新的电路迭代地更新滤波器：{overscore（h（t + 1）= {overscore（ h（t）+ mu [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {{overscore（x（t）}，其中{overscore（h（t） 表示FIR滤波器的滤波器抽头的向量{overscore（x（t））是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z ）是FIR滤波器的输出，mu确定适配的存储器或窗口大小，K是考虑到通信信道，接收机和均衡器的实际限制的比例因子，并且提供了一个过程和电路结构 用于校准比例因子K.