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公开(公告)号:US20070146011A1
公开(公告)日:2007-06-28
申请号:US11321371
申请日:2005-12-28
申请人: Frank O'Mahony , Bryan Casper , James Jaussi , Moonkyun Maeng
发明人: Frank O'Mahony , Bryan Casper , James Jaussi , Moonkyun Maeng
IPC分类号: H03K19/00
摘要: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.
摘要翻译: 这里公开了用于控制时钟信号中的占空比的占空比调整电路。 在一些实施例中,提供了包括时钟驱动器的电路,以通过时钟路径驱动差分时钟信号。 反馈电路(i)耦合到时钟路径以监视时钟信号中的偏移,以及(ii)到时钟驱动器,以基于所监视的时钟信号偏移对时钟驱动器偏移进行数字控制。 本文公开了其它实施例。
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公开(公告)号:US08571513B2
公开(公告)日:2013-10-29
申请号:US13540500
申请日:2012-07-02
申请人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号: H04B1/28
CPC分类号: H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译: 对于一个公开的实施例,集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号,而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路,其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号,并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。
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公开(公告)号:US20070115048A1
公开(公告)日:2007-05-24
申请号:US11268911
申请日:2005-11-07
申请人: Mozhgan Mansuri , Frank O'Mahony , Bryan Casper , James Jaussi
发明人: Mozhgan Mansuri , Frank O'Mahony , Bryan Casper , James Jaussi
IPC分类号: H03F1/02
CPC分类号: H03F3/45197 , H03F3/45744
摘要: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.
摘要翻译: 在一些实施例中,提供了在其输出处具有可控地可变偏移的均衡器电路。
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公开(公告)号:US20070152746A1
公开(公告)日:2007-07-05
申请号:US11323310
申请日:2005-12-30
申请人: Bryan Casper , Timothy Hollis , James Jaussi , Stephen Mooney , Frank O'Mahony , Mozhgan Mansuri
发明人: Bryan Casper , Timothy Hollis , James Jaussi , Stephen Mooney , Frank O'Mahony , Mozhgan Mansuri
IPC分类号: H03K5/00
CPC分类号: H03K5/1565 , H03H11/1291 , H03K5/01 , H03K5/1252 , H04L7/027
摘要: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.
摘要翻译: 一种可调谐带通滤波器,用于响应于输入差分时钟信号提供经滤波的差分时钟信号,其中实施例包括由可调谐负载加载的晶体管对,以及用于调谐可调负载的反馈电路。 在一些实施例中,反馈电路调谐负载以最大化小信号差分增益。 在其他实施例中,反馈电路调整负载以最小化指示经滤波的差分时钟信号中的抖动的度量。 描述和要求保护其他实施例。
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公开(公告)号:US20120281323A1
公开(公告)日:2012-11-08
申请号:US13540500
申请日:2012-07-02
申请人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号: H02H9/04
CPC分类号: H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译: 对于一个公开的实施例,集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号,而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路,其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号,并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。
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公开(公告)号:US08213894B2
公开(公告)日:2012-07-03
申请号:US11323370
申请日:2005-12-29
申请人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号: H04B1/28
CPC分类号: H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译: 对于一个公开的实施例,集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号,而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路,其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号,并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。
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公开(公告)号:US20070153445A1
公开(公告)日:2007-07-05
申请号:US11323370
申请日:2005-12-29
申请人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen Mooney
发明人: Frank O'Mahony , Bryan Casper , James Jaussi , Matthew Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen Mooney
IPC分类号: H02B1/00
CPC分类号: H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译: 对于一个公开的实施例,集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号,而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路,其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号,并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。
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公开(公告)号:US20070233444A1
公开(公告)日:2007-10-04
申请号:US11395537
申请日:2006-03-31
申请人: Frank O'Mahony , Haydar Kutuk , Bryan Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
发明人: Frank O'Mahony , Haydar Kutuk , Bryan Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
IPC分类号: G06F17/50
CPC分类号: G06F17/5036
摘要: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
摘要翻译: 通常,在一个方面,本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。 模拟器能够为晶体管以及无源元件(如电阻)增加噪声。 模拟器使用与设备并联的至少一个电流源来模拟噪声。 电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。 可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。 模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱(例如,热噪声,闪烁噪声)的任何噪声源。 模拟器与标准电路模拟器兼容。
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公开(公告)号:US09116204B2
公开(公告)日:2015-08-25
申请号:US13997604
申请日:2012-03-30
申请人: Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
发明人: Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
IPC分类号: G01R13/02 , G01R31/317 , H03K5/00
CPC分类号: G01R31/31725 , G01R25/08 , G01R31/31726 , G04F10/005 , H03K2005/00052
摘要: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.
摘要翻译: 在集成电路(IC)芯片上构造的全数字延迟测量电路(DMC)表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。 片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值,归一化为两个时钟的时钟周期。
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公开(公告)号:US06909127B2
公开(公告)日:2005-06-21
申请号:US09893023
申请日:2001-06-27
IPC分类号: H01L23/522 , H01L27/10
CPC分类号: H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
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