利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.033 秒)

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures
    1.
    发明授权
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures 有权
    形成包括高k电介质层和电极阻挡层以及相关结构的电子器件的方法

    公开(公告)号：US07244645B2

    公开(公告)日：2007-07-17

    申请号：US11479551

    申请日：2006-06-30

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
    2.
    发明授权
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
    形成包括高k电介质层和电极阻挡层的电子器件的方法

    公开(公告)号：US07148100B2

    公开(公告)日：2006-12-12

    申请号：US10969564

    申请日：2004-10-20

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers
    3.
    发明申请
    Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
    形成包括高k电介质层和电极阻挡层的电子器件的方法

    公开(公告)号：US20050082625A1

    公开(公告)日：2005-04-21

    申请号：US10969564

    申请日：2004-10-20

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Methods of forming electronic devices including high-K dielectric layers and electrode barrier layers and related structures
    4.
    发明申请
    Methods of forming electronic devices including high-K dielectric layers and electrode barrier layers and related structures 有权
    形成包括高K电介质层和电极阻挡层及相关结构的电子器件的方法

    公开(公告)号：US20060263966A1

    公开(公告)日：2006-11-23

    申请号：US11479551

    申请日：2006-06-30

    申请人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    发明人： Byung-Hee Kim ,  Gil-Heyun Choi ,  Kyung-In Choi ,  Chang-Won Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

    摘要翻译： 形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。 可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。 栅电极阻挡层和栅电极金属层可以由不同的材料形成。 此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

    Method of forming a gate of a semiconductor device
    6.
    发明申请
    Method of forming a gate of a semiconductor device 有权
    形成半导体器件的栅极的方法

    公开(公告)号：US20060110900A1

    公开(公告)日：2006-05-25

    申请号：US11283121

    申请日：2005-11-18

    申请人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Jang-Hee Lee ,  Jae-Hwa Park ,  Dong-Chan Lim ,  Byung-Hak Lee ,  Hee-Sook Park

    发明人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Jang-Hee Lee ,  Jae-Hwa Park ,  Dong-Chan Lim ,  Byung-Hak Lee ,  Hee-Sook Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28247 ,  H01L21/28044 ,  H01L29/4925

    摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

    摘要翻译： 在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。 第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。 在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。 使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。 在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。 因此，可能不会产生相邻布线之间的短路。

    Semiconductor device including an ohmic layer
    8.
    发明授权
    Semiconductor device including an ohmic layer 有权
    包括欧姆层的半导体器件

    公开(公告)号：US07875939B2

    公开(公告)日：2011-01-25

    申请号：US12453198

    申请日：2009-05-01

    申请人： Hee-Sook Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Sun-Pil Youn ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Jang-Hee Lee ,  Woong-Hee Sohn

    发明人： Hee-Sook Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Sun-Pil Youn ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Jang-Hee Lee ,  Woong-Hee Sohn

    IPC分类号： H01L23/532

    CPC分类号： H01L29/4933 ,  C23C16/42 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76846 ,  H01L29/517

    摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

    摘要翻译： 在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。 可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。 反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。 当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

    Semiconductor devices including gate structures and leakage barrier oxides
    9.
    发明授权
    Semiconductor devices including gate structures and leakage barrier oxides 有权
    包括栅极结构和漏电阻氧化物的半导体器件

    公开(公告)号：US07772637B2

    公开(公告)日：2010-08-10

    申请号：US12401087

    申请日：2009-03-10

    申请人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    发明人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28273 ,  H01L29/42324

    摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。 更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极 所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。 漏电阻氧化物可以形成在第二栅电极的侧壁上。 绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。 此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。 还讨论了相关结构。

    Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides
    10.
    发明申请
    Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides 有权
    包括栅极结构和漏极氧化物的半导体器件

    公开(公告)号：US20090173986A1

    公开(公告)日：2009-07-09

    申请号：US12401087

    申请日：2009-03-10

    申请人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    发明人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L29/42324

    摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。 更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极 所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。 漏电阻氧化物可以形成在第二栅电极的侧壁上。 绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。 此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。 还讨论了相关结构。