公开(公告)号：US20200246940A1

公开(公告)日：2020-08-06

申请号：US16471468

申请日：2017-11-21

申请人： Jang Hee LEE

发明人： Jang Hee LEE

IPC分类号： B24D18/00 ,  B24B23/02 ,  B24B45/00 ,  B29C45/14

摘要： The present invention relates to a grinding disc used in a grinder for cutting a workpiece by generating a rotation power by a motor or air pressure and, more specifically, to a grinding disc with a fixing part for a one-touch holder, which includes an abrasive part which comes into contact with a workpiece, and a fixing part formed in the center of the abrasive part for attachment and detachment with respect to a grinder, wherein the fixing part is formed by injection molding so as to improve the bonding force with the abrasive part and can be attached to or detached from the grinder by a one-touch method.

公开(公告)号：US07897500B2

公开(公告)日：2011-03-01

申请号：US12276562

申请日：2008-11-24

申请人： Eun-ji Jung ,  Dae-yong Kim ,  Gil-heyun Choi ,  Byung-hee Kim ,  Woong-hee Sohn ,  Hyun-su Kim ,  Jang-hee Lee ,  Eun-ok Lee ,  Jeong-gil Lee

发明人： Eun-ji Jung ,  Dae-yong Kim ,  Gil-heyun Choi ,  Byung-hee Kim ,  Woong-hee Sohn ,  Hyun-su Kim ,  Jang-hee Lee ,  Eun-ok Lee ,  Jeong-gil Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28052 ,  H01L29/66545

摘要： A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

摘要翻译： 多个间隔开的导体结构形成在半导体衬底上，每个导体结构包括导电层。 绝缘垫片形成在导体结构的侧壁上。 形成填充相邻绝缘间隔件之间的间隙的层间绝缘膜。 去除层间绝缘层的一部分以暴露导电层的上表面。 相应的外延层在导电层的相应暴露的上表面上生长，并且各自的外延层形成各自的金属硅化物层。

公开(公告)号：US20090256177A1

公开(公告)日：2009-10-15

申请号：US12453198

申请日：2009-05-01

申请人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

发明人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

IPC分类号： H01L29/80 ,  H01L23/498 ,  H01L23/52

CPC分类号： H01L29/4933 ,  C23C16/42 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76846 ,  H01L29/517

摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

摘要翻译： 在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。 可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。 反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。 当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

公开(公告)号：US07585787B2

公开(公告)日：2009-09-08

申请号：US11648595

申请日：2007-01-03

申请人： Tae-Ho Cha ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jang-Hee Lee ,  Geum-Jung Seong

发明人： Tae-Ho Cha ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jang-Hee Lee ,  Geum-Jung Seong

IPC分类号： H01L21/469

CPC分类号： H01L29/4941 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11568 ,  H01L29/513

摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

摘要翻译： 半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

公开(公告)号：US07534709B2

公开(公告)日：2009-05-19

申请号：US11233580

申请日：2005-09-23

申请人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Hee-Sook Park ,  Woong-Hee Sohn ,  Jong-Ryeol Yoo ,  Sun-Pil Yun ,  Jang-Hee Lee ,  Dong-Chan Lim

发明人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Hee-Sook Park ,  Woong-Hee Sohn ,  Jong-Ryeol Yoo ,  Sun-Pil Yun ,  Jang-Hee Lee ,  Dong-Chan Lim

IPC分类号： H01L21/3205

CPC分类号： H01L21/76841 ,  H01L21/28061 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L29/4933 ,  H01L29/4941

摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.

摘要翻译： 本发明的实施例包括可以制造成具有较低电阻的半导体器件，以及形成半导体器件的方法。 在多晶硅层和金属层之间形成电阻降低层。 结果，多晶硅层和金属层之间的界面电阻大大降低，并且界面电阻的分布非常均匀。 结果，包括电阻降低层的导电结构具有大大降低的薄层电阻以改善具有导电结构的半导体器件的电特性。

公开(公告)号：US20080073692A1

公开(公告)日：2008-03-27

申请号：US11773362

申请日：2007-07-03

申请人： Jang-Hee LEE ,  Geum-Jung SEONG ,  Byung-Hee KIM ,  Tae-Ho CHA ,  Hee-Sook PARK

发明人： Jang-Hee LEE ,  Geum-Jung SEONG ,  Byung-Hee KIM ,  Tae-Ho CHA ,  Hee-Sook PARK

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28061 ,  H01L29/66825

摘要： A method of forming a semiconductor device includes sequentially first and second tungsten silicide layers on a silicon layer. The first tungsten silicide layer is in a substantially amorphous state and a ratio of tungsten to silicon in the first tungsten silicide layer is about 1:4.5˜about 1:9.

摘要翻译： 形成半导体器件的方法在硅层上依次包括第一和第二硅化钨层。 第一硅化钨层处于基本非晶态，并且第一硅化钨层中钨与硅的比例为约1:4.5〜约1:9。

公开(公告)号：US20070072418A1

公开(公告)日：2007-03-29

申请号：US11524298

申请日：2006-09-21

申请人： Jang-hee Lee ,  Jae-hwa Park ,  Hee-sook Park ,  Byung-hee Kim

发明人： Jang-hee Lee ,  Jae-hwa Park ,  Hee-sook Park ,  Byung-hee Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/32053 ,  C23C16/42 ,  C23C16/4404 ,  H01L21/28061 ,  H01L29/517 ,  H01L29/6659

摘要： A method of forming a tungsten silicide layer and a related method of fabricating a semiconductor element. The method of forming the tungsten silicide layer includes forming a pre-coating layer within a CVD process chamber by injecting a tungsten source gas (A) and a silicon source gas (B) at a flow ratio (A/B) of 1/50 or less, and thereafter loading a semiconductor substrate into the CVD process chamber in which the precoating layer is formed, and injecting additional tungsten source gas and silicon source gas to form the tungsten silicide layer on the semiconductor substrate.

摘要翻译： 一种形成硅化钨层的方法和制造半导体元件的相关方法。 形成硅化钨层的方法包括通过以1/50的流量比（A / B）注入钨源气体（A）和硅源气体（B），在CVD处理室内形成预涂层 以下，然后将半导体衬底装载到其中形成预涂层的CVD处理室中，并且在半导体衬底上注入另外的钨源气体和硅源气体以形成硅化钨层。

公开(公告)号：US07124585B2

公开(公告)日：2006-10-24

申请号：US10504805

申请日：2003-02-14

申请人： Young-Min Kim ,  Dong-Gil Shin ,  Jang-Hee Lee

发明人： Young-Min Kim ,  Dong-Gil Shin ,  Jang-Hee Lee

IPC分类号： F01K7/02 ,  F01K1/00 ,  F01K7/22 ,  F01K25/10 ,  F01C1/04 ,  F01C11/00 ,  F01C21/00 ,  F04C18/04 ,  F04C23/00

CPC分类号： F01K7/00 ,  F01C11/004 ,  F01K27/00 ,  F02B53/00 ,  F04C18/0223 ,  F04C23/003 ,  F25B9/06 ,  F25B9/14 ,  F25B2309/1401

摘要： The present invention provides a scroll-type expander that simultaneously performs expansion and re-heating such that efficient expansion is realized and there is no reduction in efficiency caused by pressure loss occurring during the supply of an working fluid to the scroll-type expander, and that minimizes a difference in temperature between a stationary scroll member and a rotating scroll member, as well as a temperature distribution of a scroll wrap. The present invention also relates to a heat exchange system that uses a scroll-type expander to replace pistons in a conventional reciprocating Stirling engine or refrigerator with a pair of scroll-type compressor and expander such that the heat exchange system may be used as a Stirling engine or refrigerator. The present invention also provides a steam engine, in which a steam turbine in the conventional steam engine (Rankine system) is replaced with a scroll-type expander such that the steam cycle has both a re-heating cycle and a regeneration cycle.

摘要翻译： 本发明提供一种涡卷式膨胀机，其同时进行膨胀和再加热，从而实现有效的膨胀，并且在向涡旋式膨胀机供给工作流体期间发生的压力损失不会降低效率， 使得固定涡旋构件和旋转涡旋构件之间的温度差最小化以及涡卷的温度分布。 本发明还涉及一种热交换系统，其使用涡旋式膨胀机来代替常规的往复式斯特林发动机或冰箱中的活塞与一对涡旋式压缩机和膨胀机，使得热交换系统可用作斯特林 发动机或冰箱。 本发明还提供一种蒸汽发动机，其中常规蒸汽发动机（兰金系统）中的蒸汽轮机被涡旋式膨胀机代替，使得蒸汽循环具有再加热循环和再生循环。

公开(公告)号：US5529036A

公开(公告)日：1996-06-25

申请号：US383374

申请日：1995-02-03

申请人： Young-Il Jeong ,  Jang-Hee Lee ,  Kern-Yong Kang

发明人： Young-Il Jeong ,  Jang-Hee Lee ,  Kern-Yong Kang

IPC分类号： F01L1/38 ,  F01L3/06 ,  F02B31/00 ,  F02B75/02

CPC分类号： F01L3/06 ,  F02B2075/025 ,  F02B2275/48 ,  Y02T10/125 ,  Y02T10/146

摘要： This invention relates to a scavenging shroud mechanism for improving scavenging of a 2-stroke engine, and more particularly to a scavenging shroud mechanism for improving scavenging of a 2-stroke engine which is constructed such that a scavenging shroud mechanism is provided to a scavenging valve whereby compressed air sucked into an interior of a combustion chamber makes a tumble phenomenon along with cylinder wall surface and thereby pushes out already burned burnt gas and simultaneously is capable of efficiently feeding new air so that efficient reverse loop scavenging system is made. The scavenging shroud mechanism has a baffle 2, shroud guide notch 3 and a shroud neck 4, and a fixed supporting pin 6 and a supporting guide 5 provided on the inner side of the intake manifold 9. A shroud guide notch 3 is provided in the baffle 2 so as to permit the scavenging shroud mechanism 1 to up and down-ward movement but not right and left rotational movement.

摘要翻译： 本发明涉及一种用于改善二冲程发动机的清扫的清扫护罩机构，更具体地涉及一种用于改善二冲程发动机的扫气的扫气护罩机构，其被构造成使清扫护罩机构设置在扫气阀 吸入燃烧室内部的压缩空气与气缸壁面一起发生翻滚现象，从而推出已经燃烧的燃烧气体，同时能够有效地供给新的空气，从而形成有效的反向回路清除系统。 清扫护罩机构具有挡板2，护罩引导槽3和护罩颈部4，以及设置在进气歧管9的内侧的固定支撑销6和支撑引导件5.护罩引导槽3设置在 挡板2，以便允许扫气罩机构1向上和向下移动，但不允许左右旋转运动。

公开(公告)号：US20160064193A1

公开(公告)日：2016-03-03

申请号：US14734183

申请日：2015-06-09

申请人： Hogon KIM ,  Hyunsu KIM ,  Jang-Hee LEE ,  Gilheyun CHOI ,  Jongwon HONG

发明人： Hogon KIM ,  Hyunsu KIM ,  Jang-Hee LEE ,  Gilheyun CHOI ,  Jongwon HONG

IPC分类号： H01J37/32

CPC分类号： H01J37/32165 ,  H01J37/32091 ,  H01J37/32174

摘要： A semiconductor manufacturing apparatus includes a lower electrode, an upper electrode, first and second high-frequency power sources, and a controller. The lower electrode is disposed in a process chamber, and the upper electrode is disposed over the lower electrode in the process chamber. The first high-frequency power source is connected to one of the lower electrode and the upper electrode, and the second high-frequency power source is connected to one of the lower electrode and the upper electrode. The controller is connected to the first and second high-frequency power sources. The first high-frequency power source generates a first high-frequency power used to perform a first capacitively coupled plasma (CCP) process. The second high-frequency power source generates a second high-frequency power used to perform a second CCP process. The controller controls the second high-frequency power source to interrupt the second high-frequency power during the first CCP process.

摘要翻译： 半导体制造装置包括下电极，上电极，第一高频电源和第二高频电源以及控制器。 下电极设置在处理室中，上电极设置在处理室中的下电极之上。 第一高频电源连接到下电极和上电极中的一个，第二高频电源连接到下电极和上电极之一。 控制器连接到第一和第二高频电源。 第一高频电源产生用于执行第一电容耦合等离子体（CCP）过程的第一高频功率。 第二高频电源产生用于执行第二CCP处理的第二高频电源。 控制器控制第二高频电源，以在第一CCP过程中中断第二高频电源。