公开(公告)号：US20130037944A1

公开(公告)日：2013-02-14

申请号：US13568367

申请日：2012-08-07

申请人： Byung-Hyun Lee ,  Hoon Lee

发明人： Byung-Hyun Lee ,  Hoon Lee

IPC分类号： H01L23/488

CPC分类号： H01L24/14 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13007 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/29099 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via.

摘要翻译： 芯片堆叠封装包括第一半导体芯片，第二半导体芯片和第三半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的第一通孔硅通孔。 第二半导体芯片堆叠在第一半导体芯片上，并且包括延伸穿过第二半导体芯片的第二通孔硅通孔。 第二通硅通孔设置在第一通孔硅通孔上，并且具有小于第一通硅通孔的横截面面积。 第三半导体芯片堆叠在第一半导体芯片上，并且包括延伸穿过第三半导体芯片的第三通孔硅通孔。 第三贯通硅通孔设置在第二贯通硅通孔上，其截面积小于第二通硅通孔的横截面面积。

公开(公告)号：US09041219B2

公开(公告)日：2015-05-26

申请号：US13450164

申请日：2012-04-18

申请人： Byung-Hyun Lee ,  Hoon Lee

发明人： Byung-Hyun Lee ,  Hoon Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/525 ,  G11C29/00 ,  H01L21/66 ,  H01L25/065 ,  H01L23/00 ,  G11C5/04 ,  H01L25/18

CPC分类号： H01L23/5252 ,  G11C5/04 ,  G11C29/883 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

摘要翻译： 提供了多芯片封装。 多芯片封装包括多个芯片，其包括至少一个坏芯片和至少一个堆叠好的芯片以及穿过芯片的多个穿通电极。 包含在所述至少一个坏芯片中的逻辑电路与所述多个穿透电极中的每一个绝缘。

公开(公告)号：US09000572B2

公开(公告)日：2015-04-07

申请号：US13567394

申请日：2012-08-06

申请人： Hoon Lee ,  Sang-Bo Lee

发明人： Hoon Lee ,  Sang-Bo Lee

IPC分类号： H01L23/02 ,  H01L21/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17517 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.

摘要翻译： 半导体封装基板可以包括第一半导体芯片，第二半导体芯片，插头和互连端子。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第一和第二半导体芯片可以具有对应的第一区域和对应的第二区域。 导电插头可以仅构建在第一半导体芯片的第一区域中。 第二半导体芯片的电路只能通过对应于第一和第二半导体芯片的第一区域的导电连接器与第一半导体芯片电连接。

公开(公告)号：US08976713B2

公开(公告)日：2015-03-10

申请号：US13564367

申请日：2012-08-01

申请人： Seungjae Bahng ,  Hoon Lee

发明人： Seungjae Bahng ,  Hoon Lee

IPC分类号： H01Q21/06 ,  H01Q3/00 ,  H04B7/02 ,  H04L27/00 ,  H04B1/38 ,  H04M1/00 ,  H04B7/10 ,  H04L27/233 ,  H01Q3/08

CPC分类号： H04B7/10 ,  H01Q3/08 ,  H04L27/2332

摘要： There are provided a method and apparatus for transmitting and receiving signals in the same frequency band at the same time. A signal is received using a dual polarization antenna, the main axis of the polarization of the reception signal is predicted by performing adaptive polarization tracking, and polarization filtering is performed in order to remove interference. A signal is transmitted through a polarization completely orthogonal to the tracked polarization. In accordance with the present invention, in a wireless communication system, signals can be transmitted and received in the same frequency band at the same time.

摘要翻译： 提供了一种在同一频带内发送和接收信号的方法和装置。 使用双极化天线接收信号，通过执行自适应偏振跟踪来预测接收信号的极化的主轴，并执行偏振滤波以消除干扰。 通过与跟踪的极化完全正交的偏振来传输信号。 根据本发明，在无线通信系统中，可以同时在相同频带中发送和接收信号。

公开(公告)号：US08552569B2

公开(公告)日：2013-10-08

申请号：US13517888

申请日：2012-06-14

申请人： Hoon Lee

发明人： Hoon Lee

IPC分类号： H01L29/66

CPC分类号： H01L23/5252 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/62 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13009 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/00

摘要： A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die.

摘要翻译： 叠层半导体器件包括第一半导体管芯，其具有电耦合到衬底焊盘的前侧，衬底焊盘连接到外部，第一半导体管芯的背面，第一集成电路，第一ESD和TSV，以及 TSV耦合到第一集成电路和第一ESD。 第二半导体管芯堆叠在第一半导体管芯的背面之上，第二半导体管芯包括与TSV和第二ESD电连接的第二集成电路，并且第二ESD与TSV电断开。 TSV穿透第一半导体管芯并延伸到第一半导体管芯的背面。

公开(公告)号：US08452499B2

公开(公告)日：2013-05-28

申请号：US13218130

申请日：2011-08-25

申请人： Timothy Lorentz ,  Mathew Guldan ,  Hoon Lee

发明人： Timothy Lorentz ,  Mathew Guldan ,  Hoon Lee

IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F19/00

CPC分类号： F16H61/0248 ,  F16H61/0059 ,  F16H2059/088 ,  Y10T477/70 ,  Y10T477/78

摘要： A control system for a transmission engages three clutches to create braking within the transmission to slow a machine during a shuttle shifting operation. The control system may apply the clutches so as to allocate wear between the clutches equally or unequally, as desired.

摘要翻译： 用于变速器的控制系统接合三个离合器以在变速器内产生制动以在换档操作期间减慢机器。 控制系统可以应用离合器，以便根据需要在离合器之间分配或不平等地分配磨损。

公开(公告)号：US20110310649A1

公开(公告)日：2011-12-22

申请号：US13218646

申请日：2011-08-26

申请人： Uk-song Kang ,  Hoe-Ju Chung ,  Jang-Seok Choi ,  Hoon Lee

发明人： Uk-song Kang ,  Hoe-Ju Chung ,  Jang-Seok Choi ,  Hoon Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C8/12 ,  G11C8/18 ,  G11C29/14 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

摘要翻译： 三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。 通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。 主芯片包括用于增加存储器模块/系统容量的存储器核心。 此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

公开(公告)号：US07751410B2

公开(公告)日：2010-07-06

申请号：US11635774

申请日：2006-12-07

申请人： Hoon Lee ,  Tae Whan Yoo ,  Jung Hak Kim ,  Yool Kwon ,  Bong Tae Kim

发明人： Hoon Lee ,  Tae Whan Yoo ,  Jung Hak Kim ,  Yool Kwon ,  Bong Tae Kim

IPC分类号： H04L12/46

CPC分类号： H04L47/10 ,  H04L12/4645 ,  H04L12/66 ,  H04L47/20 ,  H04L61/103 ,  H04L61/6022

摘要： An apparatus and method for managing traffic using a VID in EPON are provided. The apparatus includes a MAC lookup table, a service classification policy table, a service control policy table, a MAC lookup unit, a first and second classification module, a VID learning unit and a first and second service control module. The apparatus classifies all packets of up/downlink transmission flow using a VID into a VID unit, through the first and second classification modules and manages traffic thereof according to the parameters thereof through the first and second service control modules. Accordingly, a large amount of traffic for numerous subscribers and services thereof, which was cannot be processed by the limitation on embodying a typical switch or router, can be processed according to the present invention.

摘要翻译： 提供了一种用于使用EPON中的VID来管理业务的装置和方法。 该装置包括MAC查找表，服务分类策略表，服务控制策略表，MAC查找单元，第一和第二分类模块，VID学习单元和第一和第二服务控制模块。 该装置通过第一和第二分类模块，使用VID将上行/下行链路传输流的所有数据包分类为VID单元，并通过第一和第二服务控制模块根据其参数来管理其流量。 因此，根据本发明，可以处理不能通过实施典型交换机或路由器的限制来处理大量用户和其服务的大量业务。

公开(公告)号：US20100154455A1

公开(公告)日：2010-06-24

申请号：US11990087

申请日：2007-03-08

申请人： Seok-Mann Yoon ,  Dae-Young Lee ,  Hoon Lee ,  Chang-Ku Kang ,  Sung-Ook Jeong

发明人： Seok-Mann Yoon ,  Dae-Young Lee ,  Hoon Lee ,  Chang-Ku Kang ,  Sung-Ook Jeong

IPC分类号： F25B15/00 ,  F23L15/02 ,  F28D15/00

CPC分类号： F24F3/1423 ,  F24F2203/1024 ,  F24F2203/1028 ,  F24F2203/1032 ,  F24F2203/104 ,  F24F2203/1072 ,  F24F2203/1084

摘要： Disclosed is a dehumidifying cooling device for district heating which comprises; a case having a first partition to divide the interior of the case into a wet channel and a dry channel and a second partition to divided the wet channel into a first wet channel and a second wet channel, a sensible heat exchanger to heat exchange the outside air in the first wet channel with the outside air in the second wet channel, a heating coil for raising the temperature of the outside air in the second wet channel, a rotatable de humidifying wheel for adsorbing and removing moisture contained in the circulated air within the dry channel, and a regenerative-evaporative cooler for cooling the circulated air in the dry channel. With this configuration, the device can carry out an air cooling operation by use of hot water supplied by district heating systems and gas or oil boilers installed in individual households, thereby achieving a reduced device size via the implementation of the cooling operation under the atmospheric pressure state and reducing manufacturing costs by virtue of a simplified system configuration.

摘要翻译： 公开了一种用于区域供热的除湿冷却装置，包括： 壳体具有将壳体内部分成湿通道的第一隔板和干燥通道以及将湿通道分成第一湿通道和第二湿通道的第二隔板，显热交换器以热交换外部 第一湿通道中的空气与第二湿通道中的外部空气连通，用于升高第二湿通道中的外部空气的温度的加热线圈，用于吸收和去除包含在第二湿通道内的循环空气中的水分的可旋转脱湿轮 干通道和用于冷却干燥通道中的循环空气的再生蒸发冷却器。 通过这样的结构，能够通过使用由各个家庭中安装的区域供暖系统和燃气或油锅炉供给的热水进行制冷运转，通过在大气压下实施冷却运转来实现装置尺寸的缩小 凭借简化的系统配置降低制造成本。

公开(公告)号：US20100001379A1

公开(公告)日：2010-01-07

申请号：US12458124

申请日：2009-07-01

申请人： Hoon Lee ,  Kang-wook Lee ,  Uk-song Kang

发明人： Hoon Lee ,  Kang-wook Lee ,  Uk-song Kang

IPC分类号： H01L29/40 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L23/5286 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network.

摘要翻译： MCP包括多个半导体存储器件，所述多个半导体存储器件被堆叠以限定三维（3D）结构，以及网格结构，所述网格结构互连所述多个半导体存储器件以限定3D网状结构， 基于配电网络。