公开(公告)号：US11876064B2

公开(公告)日：2024-01-16

申请号：US17429305

申请日：2020-06-15

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/13005 ,  H01L2224/2745 ,  H01L2224/2902

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

公开(公告)号：US12211813B2

公开(公告)日：2025-01-28

申请号：US17648307

申请日：2022-01-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling-Yi Chuang

IPC: H01L23/00 ,  H01L23/48

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip, where a first conductive connection wire of the first chip is connected to a first conductive contact pad, a second conductive connection wire of the second chip is connected to a second conductive contact pad, the first conductive contact pad includes a first conductor group and a first connection group, and the second conductive contact pad includes a second conductor group and a second connection group.

公开(公告)号：US11984417B2

公开(公告)日：2024-05-14

申请号：US17648309

申请日：2022-01-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling-Yi Chuang

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/03 ,  H01L2224/0331 ,  H01L2224/03462 ,  H01L2224/05013 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/05564 ,  H01L2224/05578 ,  H01L2224/05601 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05638 ,  H01L2224/08145 ,  H01L2224/08503 ,  H01L2224/8081

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.

公开(公告)号：US20220115352A1

公开(公告)日：2022-04-14

申请号：US17429592

申请日：2020-06-15

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang

IPC: H01L23/00 ,  H01L21/306

Abstract: The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

公开(公告)号：US11973045B2

公开(公告)日：2024-04-30

申请号：US17650796

申请日：2022-02-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling-Yi Chuang

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/039 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/08147 ,  H01L2224/80895

Abstract: A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.

公开(公告)号：US20240055399A1

公开(公告)日：2024-02-15

申请号：US18446512

申请日：2023-08-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kaimin LV ,  Ling-Yi Chuang

IPC: H01L25/065 ,  H01L23/538 ,  H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/5386 ,  H10B80/00 ,  H01L23/5384 ,  H01L24/48 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L25/50 ,  H01L2224/48235 ,  H01L2224/08137

Abstract: A semiconductor structure, a method for manufacturing same, and a semiconductor device are provided. The semiconductor structure includes: a substrate having a groove and power supply pins; a storage module located in the groove; in which the storage module includes a plurality of storage chips stacked in a first direction, the first direction being parallel to the bottom surface of the groove; power supply signal lines being provided in each of the storage chips, and at least one of the plurality of storage chips having a power supply wiring layer electrically connected to the power supply signal lines; and conductive parts connected with the power supply wiring layer and the power supply pins.

公开(公告)号：US20220148990A1

公开(公告)日：2022-05-12

申请号：US17429305

申请日：2020-06-15

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang

IPC: H01L23/00

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

公开(公告)号：US11855032B2

公开(公告)日：2023-12-26

申请号：US17429592

申请日：2020-06-15

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang

IPC: H01L23/00 ,  H01L21/306

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/13006 ,  H01L2224/13026 ,  H01L2224/1354 ,  H01L2224/81815

Abstract: The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

公开(公告)号：US11545468B2

公开(公告)日：2023-01-03

申请号：US17202248

申请日：2021-03-15

Applicant: Changxin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang ,  Shu-Liang Ning

IPC: H01L21/768 ,  H01L25/065 ,  H01L21/78 ,  H01L23/48 ,  H01L23/544 ,  H01L25/00

Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer, wherein an upper surface of the first wafer includes a first bonding pad configured to connect to a first signal; fabricating a first redistribution layer (RDL) on the first wafer, comprising a first wiring electrically connected to the first bonding pad, and the first wiring includes a first landing pad; bonding a second wafer on the first RDL, wherein the second wafer includes a second bonding pad configured to connect the first signal and located corresponding to the first bonding pad; fabricating a first through silicon via (TSV) with a bottom connected to the first landing pad at a position corresponding to the first landing pad; and fabricating a second RDL on the second wafer to connect the second bonding pad and the first TSV. This wafer stacking method improves the manufacturing yield.

公开(公告)号：US11348873B2

公开(公告)日：2022-05-31

申请号：US17102182

申请日：2020-11-23

Applicant: Changxin Memory Technologies, Inc.

Inventor： Ling-Yi Chuang ,  Shu-Liang Ning

IPC: H01L21/50 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.