公开(公告)号：US06194301B1

公开(公告)日：2001-02-27

申请号：US09352318

申请日：1999-07-12

申请人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

发明人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545

摘要： An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

摘要翻译： 提出了一种集成电路器件。 本发明的集成电路器件包括半导体衬底，该半导体衬底具有使用用于自对准扩散接触（SAC）的常规绝缘栅极叠层形成的晶体管栅极的组合以及通过去除电介质帽形成的晶体管栅极结构 栅堆叠从半导体衬底的选定区域，并用第二栅极导体代替介质帽栅极堆叠，第二栅极导体使用镶嵌工艺进行图案化。

公开(公告)号：US06190979B1

公开(公告)日：2001-02-20

申请号：US09351148

申请日：1999-07-12

申请人： Carl Radens ,  Mary E. Weybright

发明人： Carl Radens ,  Mary E. Weybright

IPC分类号： H01L2122

CPC分类号： H01L21/823842 ,  H01L21/2255 ,  H01L21/28035

摘要： A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance. The method comprises depositing a conformal dopant source so as to provide gap fill between gate stack conductors in the narrow space array regions and under fill between gate stack conductors in the wide space array regions; etching so that the conformal dopant source is removed from the wide space array regions and remains at least in part between the gate stack conductors in the narrow space array regions; and counter-doping gate stack conductors in the narrow space array regions by lateral diffusion of dopant from conformal dopant source through narrow space array gate stack conductor sidewalls.

摘要翻译： 一种用于在半导体衬底上反向掺杂栅极叠层导体的方法，该衬底设置有具有间隔开第一距离的多个封盖栅叠层导体的窄空间阵列区域（即，存储器件区域）和宽空间阵列区域 即逻辑器件区域），其具有间隔第二距离的多个栅叠层导体，其中第一距离相对于第二距离窄。 该方法包括沉积共形掺杂剂源，以便在窄空间阵列区域中提供栅极堆叠导体之间的间隙填充，并在宽空间阵列区域中的栅极堆叠导体之间填充; 蚀刻，使得保形掺杂剂源从宽空间阵列区域移除并且至少部分地保留在窄空间阵列区域中的栅极堆叠导体之间; 和反掺杂栅极叠层导体，通过掺杂剂从共形掺杂剂源通过窄空间阵列栅叠层导体侧壁的横向扩散而在窄空间阵列区域中。

公开(公告)号：US06388294B1

公开(公告)日：2002-05-14

申请号：US09718571

申请日：2000-11-22

申请人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

发明人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545

摘要： An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

摘要翻译： 提出了一种集成电路器件。 本发明的集成电路器件包括半导体衬底，该半导体衬底具有使用用于自对准扩散接触（SAC）的常规绝缘栅极叠层形成的晶体管栅极的组合以及通过去除电介质帽形成的晶体管栅极结构 栅堆叠从半导体衬底的选定区域，并用第二栅极导体代替介质帽栅极堆叠，第二栅极导体使用镶嵌工艺进行图案化。

公开(公告)号：US06403423B1

公开(公告)日：2002-06-11

申请号：US09713272

申请日：2000-11-15

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：US06380027B2

公开(公告)日：2002-04-30

申请号：US09225127

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

发明人： Toshiharu Furukawa ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti ,  Mary E. Weybright

IPC分类号： H01L21242

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10894

摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

摘要翻译： 用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及 其中所述第一氧化物比所述第二氧化物厚。

公开(公告)号：US06346734B2

公开(公告)日：2002-02-12

申请号：US09325942

申请日：1999-06-04

申请人： Ramachandra Divakaruni ,  Mary E. Weybright

发明人： Ramachandra Divakaruni ,  Mary E. Weybright

IPC分类号： H01L2976

CPC分类号： H01L21/28061 ,  H01L27/10873 ,  Y10S257/90

摘要： A semiconductor device includes a semiconductor substrate having an oxide layer thereon. A gate conductor is provided on the oxide layer, the gate conductor including a layer of polysilicon on the oxide layer, a tungsten silicide layer on the polysilicon layer, and a nitride cap layer on the tungsten silicide layer. The polysilicon layer has a length greater than length of the silicide layer and the nitride layer. Dielectric spacers on the gate conductor overlay the nitride cap layer and the tungsten silicide layer to provide a sidewall substantially flush with the polysilicon layer. Exposed polysilicon on the polysilicon layer is oxidized.

摘要翻译： 半导体器件包括其上具有氧化物层的半导体衬底。 栅极导体设置在氧化物层上，栅极导体包括氧化物层上的多晶硅层，多晶硅层上的硅化钨层和硅化钨层上的氮化物覆盖层。 多晶硅层的长度大于硅化物层和氮化物层的长度。 栅极导体上的介质间隔物覆盖氮化物覆盖层和硅化钨层，以提供与多晶硅层基本齐平的侧壁。 多晶硅层上的暴露的多晶硅被氧化。

公开(公告)号：US06724053B1

公开(公告)日：2004-04-20

申请号：US09511395

申请日：2000-02-23

申请人： Rama Divakaruni ,  Ryota Katsumata ,  Giuseppe La Rosa ,  Rajesh Rengarajan ,  Mary E. Weybright

发明人： Rama Divakaruni ,  Ryota Katsumata ,  Giuseppe La Rosa ,  Rajesh Rengarajan ,  Mary E. Weybright

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/7838

摘要： P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）器件具有被称为阈值电压的特性。 该阈值电压可以由与器件的栅极区域的主要部分和器件的侧壁角相关联的单独的阈值电压组成。 在某些情况下，设备的侧壁角区域中的阈值行为可能主导设备的性能，而不一定是设备设计者所期望的方式。 描述了一种控制阈值电压特性的方法。 特别地，器件的栅极侧壁区域中的氮的离子注入可以提供这种控制。 还描述了通过该方法制造的装置。

公开(公告)号：US06548357B2

公开(公告)日：2003-04-15

申请号：US10117869

申请日：2002-04-08

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：US06197632B1

公开(公告)日：2001-03-06

申请号：US09440776

申请日：1999-11-16

申请人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

发明人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L29/6659

摘要： This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips. An IC fabrication is provided, according to an aspect of the invention, including a silicon wafer, a DRAM array fabrication disposed on said silicon wafer having a first multitude of gate sidewall oxides, and a logic support device fabrication disposed on said wafer adjacent said DRAM array fabrication and having a second multitude of gate sidewall oxides, said first multitude of gate sidewall oxides being substantially thicker than said second multitude of gate sidewall oxides. Methods of making IC fabrications according to the invention are also provided.

摘要翻译： 本发明涉及集成电路产品和工艺。 更具体地，本发明涉及高性能动态随机存取存储器（DRAM）芯片和用于制造这种芯片的过程。 提供根据本发明的一个方面的IC制造，包括硅晶片，设置在具有第一多个栅极侧壁氧化物的所述硅晶片上的DRAM阵列制造，以及设置在与所述DRAM相邻的所述晶片上的逻辑支持器件制造 阵列制造并具有第二多个栅极侧壁氧化物，所述第一多个栅极侧壁氧化物基本上比所述第二多个栅极侧壁氧化物厚。 还提供了制造根据本发明的IC制造的方法。