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161 条记录 (耗时 0.029 秒)

    Method of fabricating an integrated circuit of logic and memory using damascene gate structure
    1.
    发明授权
    Method of fabricating an integrated circuit of logic and memory using damascene gate structure 失效
    使用镶嵌门结构制造逻辑和存储器的集成电路的方法

    公开(公告)号：US06194301B1

    公开(公告)日：2001-02-27

    申请号：US09352318

    申请日：1999-07-12

    申请人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

    发明人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545

    摘要： An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

    摘要翻译： 提出了一种集成电路器件。 本发明的集成电路器件包括半导体衬底，该半导体衬底具有使用用于自对准扩散接触（SAC）的常规绝缘栅极叠层形成的晶体管栅极的组合以及通过去除电介质帽形成的晶体管栅极结构 栅堆叠从半导体衬底的选定区域，并用第二栅极导体代替介质帽栅极堆叠，第二栅极导体使用镶嵌工艺进行图案化。

    Integrated circuit using damascene gate structure
    2.
    发明授权
    Integrated circuit using damascene gate structure 失效
    集成电路采用镶嵌门结构

    公开(公告)号：US06388294B1

    公开(公告)日：2002-05-14

    申请号：US09718571

    申请日：2000-11-22

    申请人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

    发明人： Carl Radens ,  Mary E. Weybright ,  Gary Bronner

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545

    摘要： An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

    摘要翻译： 提出了一种集成电路器件。 本发明的集成电路器件包括半导体衬底，该半导体衬底具有使用用于自对准扩散接触（SAC）的常规绝缘栅极叠层形成的晶体管栅极的组合以及通过去除电介质帽形成的晶体管栅极结构 栅堆叠从半导体衬底的选定区域，并用第二栅极导体代替介质帽栅极堆叠，第二栅极导体使用镶嵌工艺进行图案化。

    Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill
    3.
    发明授权
    Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill 失效
    使用反掺杂和间隙填充在半导体衬底上制造双功函数器件的方法

    公开(公告)号：US06190979B1

    公开(公告)日：2001-02-20

    申请号：US09351148

    申请日：1999-07-12

    申请人： Carl Radens ,  Mary E. Weybright

    发明人： Carl Radens ,  Mary E. Weybright

    IPC分类号： H01L2122

    CPC分类号： H01L21/823842 ,  H01L21/2255 ,  H01L21/28035

    摘要： A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance. The method comprises depositing a conformal dopant source so as to provide gap fill between gate stack conductors in the narrow space array regions and under fill between gate stack conductors in the wide space array regions; etching so that the conformal dopant source is removed from the wide space array regions and remains at least in part between the gate stack conductors in the narrow space array regions; and counter-doping gate stack conductors in the narrow space array regions by lateral diffusion of dopant from conformal dopant source through narrow space array gate stack conductor sidewalls.

    摘要翻译： 一种用于在半导体衬底上反向掺杂栅极叠层导体的方法，该衬底设置有具有间隔开第一距离的多个封盖栅叠层导体的窄空间阵列区域（即，存储器件区域）和宽空间阵列区域 即逻辑器件区域），其具有间隔第二距离的多个栅叠层导体，其中第一距离相对于第二距离窄。 该方法包括沉积共形掺杂剂源，以便在窄空间阵列区域中提供栅极堆叠导体之间的间隙填充，并在宽空间阵列区域中的栅极堆叠导体之间填充; 蚀刻，使得保形掺杂剂源从宽空间阵列区域移除并且至少部分地保留在窄空间阵列区域中的栅极堆叠导体之间; 和反掺杂栅极叠层导体，通过掺杂剂从共形掺杂剂源通过窄空间阵列栅叠层导体侧壁的横向扩散而在窄空间阵列区域中。

    Method of fabricating vertical body-contacted SOI transistor
    4.
    发明申请
    Method of fabricating vertical body-contacted SOI transistor 失效
    垂直体接触SOI晶体管的制造方法

    公开(公告)号：US20080102569A1

    公开(公告)日：2008-05-01

    申请号：US12002828

    申请日：2007-12-19

    申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

    摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

    摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

    VERTICAL BODY-CONTACTED SOI TRANSISTOR
    5.
    发明申请
    VERTICAL BODY-CONTACTED SOI TRANSISTOR 有权
    垂直接触式SOI晶体管

    公开(公告)号：US20060175660A1

    公开(公告)日：2006-08-10

    申请号：US10906238

    申请日：2005-02-10

    申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

    摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

    摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI
    6.
    发明申请
    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
    在SOI上用于eDRAM的盒式垂直晶体管

    公开(公告)号：US20050247966A1

    公开(公告)日：2005-11-10

    申请号：US10709450

    申请日：2004-05-06

    申请人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

    摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

    摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

    DRAM cell with buried collar and self-aligned buried strap
    8.
    发明申请
    DRAM cell with buried collar and self-aligned buried strap 失效
    DRAM电池带有埋入式和自对准埋地带

    公开(公告)号：US20050093044A1

    公开(公告)日：2005-05-05

    申请号：US10696151

    申请日：2003-10-29

    申请人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bronner ,  Carl Radens ,  Oleg Gluschenkov

    发明人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bronner ,  Carl Radens ,  Oleg Gluschenkov

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/1087 ,  H01L27/10864 ,  H01L27/10867

    摘要： In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.

    摘要翻译： 在具有沟槽的DRAM单元，单元电容器和单元晶体管中，节点导电元件将单元电容器连接到单元晶体管，并且环绕节点导电元件设置套环。 轴环至少部分地设置在衬底中，直到完全在沟槽的外部。 因为套环设置在沟槽外部的衬底中，所以不限制沟槽开口的尺寸。 这使得能够使用与当前DRAM工艺步骤兼容的技术的100nm以下的沟槽。 带子被嵌入到衣领的顶表面中。

    Pattern formation employing self-assembled material
    10.
    发明授权
    Pattern formation employing self-assembled material 有权
    采用自组装材料的图案形成

    公开(公告)号：US08215074B2

    公开(公告)日：2012-07-10

    申请号：US12026123

    申请日：2008-02-05

    申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

    发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

    IPC分类号： E04B2/00

    CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

    摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

    摘要翻译： 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。 每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。