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    Method of fabricating a semiconductor device comprising high and low density patterned contacts
    1.
    发明授权
    Method of fabricating a semiconductor device comprising high and low density patterned contacts 失效
    制造包括高和低密度图案化触点的半导体器件的方法

    公开(公告)号：US07781330B2

    公开(公告)日：2010-08-24

    申请号：US11878508

    申请日：2007-07-25

    申请人： Chae-Iyoung Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

    发明人： Chae-Iyoung Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7688 ,  Y10S438/947

    摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

    摘要翻译： 提供制造半导体器件的方法。 所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。 第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。 多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。 第一接触掩模层可以形成在第一区域中。 第一虚拟掩模层可以形成在第二区域中。 可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。 可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。 可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

    Method of fabricating a semiconductor device
    2.
    发明申请
    Method of fabricating a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US20080206985A1

    公开(公告)日：2008-08-28

    申请号：US11878508

    申请日：2007-07-25

    申请人： Chae-Iyoung Kim ,  Chang-Ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

    发明人： Chae-Iyoung Kim ,  Chang-Ki Hong ,  Bo-un Yoon ,  Sung-ho Shin ,  Byoung-ho Kwon

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7688 ,  Y10S438/947

    摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

    摘要翻译： 提供制造半导体器件的方法。 所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。 第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。 多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。 第一接触掩模层可以形成在第一区域中。 第一虚拟掩模层可以形成在第二区域中。 可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。 可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。 可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

    Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same
    3.
    发明授权
    Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same 有权
    制造非易失性存储器集成电路器件的方法和使用其制造的非易失性存储器集成电路器件

    公开(公告)号：US08030150B2

    公开(公告)日：2011-10-04

    申请号：US12397543

    申请日：2009-03-04

    申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

    Method of Fabricating Non-Volatile Memory Integrated Circuit Device and Non-Volatile Memory Integrated Circuit Device Fabricated Using the Same
    5.
    发明申请
    Method of Fabricating Non-Volatile Memory Integrated Circuit Device and Non-Volatile Memory Integrated Circuit Device Fabricated Using the Same 有权
    制造非易失性存储器集成电路器件和使用其的非易失性存储器集成电路器件的方法

    公开(公告)号：US20080017915A1

    公开(公告)日：2008-01-24

    申请号：US11763137

    申请日：2007-06-14

    申请人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    发明人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    IPC分类号： H01L27/105 ,  H01L21/8229

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

    Semiconductor device including dummy gate part and method of fabricating the same
    7.
    发明授权
    Semiconductor device including dummy gate part and method of fabricating the same 有权
    半导体器件包括伪栅极部分及其制造方法

    公开(公告)号：US08053845B2

    公开(公告)日：2011-11-08

    申请号：US12291211

    申请日：2008-11-07

    申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    IPC分类号： H01L21/70

    CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

    摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

    METHOD OF FABRICATING NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE AND NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE FABRICATED USING THE SAME
    8.
    发明申请
    METHOD OF FABRICATING NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE AND NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE FABRICATED USING THE SAME 有权
    制造非易失性存储器集成电路装置的方法和使用其制造的非易失性存储器集成电路装置

    公开(公告)号：US20090159952A1

    公开(公告)日：2009-06-25

    申请号：US12397543

    申请日：2009-03-04

    申请人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    发明人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

    IPC分类号： H01L29/68

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。