公开(公告)号：US20150123284A1

公开(公告)日：2015-05-07

申请号：US14470366

申请日：2014-08-27

Applicant: Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

Inventor： Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

公开(公告)号：US20100013094A1

公开(公告)日：2010-01-21

申请号：US12503274

申请日：2009-07-15

Applicant: Chajea JO ,  Uihyoung LEE ,  Jae-hyun PHEE ,  Jeong-Woo PARK ,  Ha-Young YIM

Inventor： Chajea JO ,  Uihyoung LEE ,  Jae-hyun PHEE ,  Jeong-Woo PARK ,  Ha-Young YIM

IPC: H01L23/498

CPC classification number: H01L21/563 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11505 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/14104 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.

Abstract translation: 半导体封装以及半导体封装的制造方法。 半导体封装包括基板，其包括多个焊盘和均匀地设置在基板的整个区域上的多个凸块，而与多个焊盘的布置无关。 根据本发明，可以实现工艺的简化，可以降低工艺成本，可以提高可靠性，并且能够容易地进行填充不足。