公开(公告)号：US20120280382A1

公开(公告)日：2012-11-08

申请号：US13461949

申请日：2012-05-02

Applicant: Yunhyeok IM ,  Kyol PARK ,  Taeje CHO

Inventor： Yunhyeok IM ,  Kyol PARK ,  Taeje CHO

IPC: H01L23/373

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.

Abstract translation: 提供半导体封装。 在一个实施例中，半导体封装可以包括诸如电路基板的基板，安装在电路基板上的半导体芯片，覆盖半导体芯片和电路基板并包括第一温度控制构件的模制件（或密封剂），以及 覆盖模制件的散热构件。

公开(公告)号：US20120175782A1

公开(公告)日：2012-07-12

申请号：US13347270

申请日：2012-01-10

Applicant: Yunhyeok Im ,  Tae Hong Min ,  Taeje Cho

Inventor： Yunhyeok Im ,  Tae Hong Min ,  Taeje Cho

IPC: H01L23/522

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Abstract translation: 提供半导体封装及其制造方法。 包括第一面和第二面的衬底，其中所述第一面和所述第二面彼此面对; 设置在第一面上的第一接地图案​​; 设置在所述第二面上的第二接地图案; 多个接地通孔插头，其连接第一接地图案​​和第二接地图案，其中多个接地通孔插头穿透基板; 以及插入在所述多个接地通孔插头之间的第一氧化铝膜，其中通过插头将多个接地电压施加接地电压。 半导体封装可以使用阳极氧化工艺制造。

公开(公告)号：US20120119346A1

公开(公告)日：2012-05-17

申请号：US13243996

申请日：2011-09-23

Applicant: YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

Inventor： YUNHYEOK IM ,  Chungsun Lee ,  Taeje Cho

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/29 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00

Abstract: Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a package cap which is capable of radiating high temperatures and performs a shield function preventing transmission of electromagnetic waves into and/or out of the semiconductor package. The semiconductor package including the package cap prevents chip malfunctions and improves device reliability. The package cap is positioned to cover first and second semiconductor chips of a semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法。 半导体封装包括封装帽，其能够辐射高温并执行屏蔽功能，防止电磁波进入和/或流出半导体封装。 包括封装盖的半导体封装防止芯片故障并提高器件的可靠性。 封装帽定位成覆盖半导体封装的第一和第二半导体芯片。

公开(公告)号：US20110133333A1

公开(公告)日：2011-06-09

申请号：US12951140

申请日：2010-11-22

Applicant: Woonseong Kwon ,  Hyuekjae Lee ,  Taeje Cho ,  Yonghwan Kwon ,  Jung-Hwan Kim ,  Chiyoung Lee ,  Taeeun Kim

Inventor： Woonseong Kwon ,  Hyuekjae Lee ,  Taeje Cho ,  Yonghwan Kwon ,  Jung-Hwan Kim ,  Chiyoung Lee ,  Taeeun Kim

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/732 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices include a conductive via that extends into a substrate face and that also protrudes beyond the substrate face to define a conductive via end surface and a conductive via sidewall that extends from the end surface towards the substrate face. A conductive cap is provided on the end surface, the conductive cap including a conductive cap body that extends across the end surface and a flange that extends from the conductive cap body along the conductive via sidewall towards the substrate face. Related fabrication methods are also described.

Abstract translation: 微电子器件包括延伸到衬底表面中并且还突出超过衬底表面以限定导电通孔端表面的导电通孔和从端表面朝向衬底面延伸的导电通孔侧壁。 导电盖设置在端表面上，导电盖包括延伸穿过端表面的导电盖本体和从导电盖主体沿着导电通孔侧壁朝向衬底面延伸的凸缘。 还描述了相关的制造方法。

公开(公告)号：US10186500B2

公开(公告)日：2019-01-22

申请号：US15357741

申请日：2016-11-21

Applicant: Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC: H01L25/10 ,  H01L25/00

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US20160148888A1

公开(公告)日：2016-05-26

申请号：US14948228

申请日：2015-11-20

Applicant: Seung-Kwan RYU ,  Jongbo SHIM ,  Eunchul AHN ,  Taeje CHO

Inventor： Seung-Kwan RYU ,  Jongbo SHIM ,  Eunchul AHN ,  Taeje CHO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06517 ,  H01L2224/09519 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81444 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer.

Abstract translation: 半导体器件可以包括半导体衬底，半导体衬底上的导电焊盘，覆盖半导体衬底并暴露导电焊盘的钝化层和凸块结构。 凸块结构可以包括导电焊盘上的第一凸起结构和钝化层上的第二凸起结构。 第一凸块结构可以包括顺序地堆叠在导电焊盘上的基底凸起层，第一柱凸起层和第一焊料凸块层。 第二凸起结构可以包括顺序地堆叠在钝化层上的第二柱状凸起层和第二焊料凸块层。

公开(公告)号：US20160079208A1

公开(公告)日：2016-03-17

申请号：US14821767

申请日：2015-08-09

Applicant: Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

Inventor： Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8113 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/17136 ,  H01L2224/17179

Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

Abstract translation: 一个实施例包括半导体封装，包括：衬底; 安装在所述基板上的第一半导体芯片; 安装在所述第一半导体芯片的顶表面上的第二半导体芯片; 设置在所述第一和第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片的连接凸块; 以及第一散热部，其设置在第一和第二半导体芯片之间的第一半导体芯片的顶表面上并且与第二半导体芯片的底表面间隔开。

公开(公告)号：US08558371B2

公开(公告)日：2013-10-15

申请号：US13011286

申请日：2011-01-21

Applicant: JiSun Hong ,  Taeje Cho ,  Un-Byoung Kang ,  Hyuekjae Lee ,  Youngbok Kim ,  Hyung-sun Jang

Inventor： JiSun Hong ,  Taeje Cho ,  Un-Byoung Kang ,  Hyuekjae Lee ,  Youngbok Kim ,  Hyung-sun Jang

IPC: H01L23/12

CPC classification number: H01L23/3114 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

Abstract translation: 提供了一种晶片级封装方法和使用其制造的半导体器件。 在该方法中，提供包括多个芯片的基板。 在对应于多个芯片的边界的基板上形成粘合剂层。 覆盖基板的上部并且具有至少一个露出多个芯片之间的边界处的粘合剂层或基板的开口的盖板附接到粘合剂层。

公开(公告)号：US09793165B2

公开(公告)日：2017-10-17

申请号：US13345441

申请日：2012-01-06

Applicant: Seyoung Jeong ,  Taeje Cho ,  Hogeon Song ,  Kyu-Ha Lee

Inventor： Seyoung Jeong ,  Taeje Cho ,  Hogeon Song ,  Kyu-Ha Lee

IPC: H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05109 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.

公开(公告)号：US20170004990A1

公开(公告)日：2017-01-05

申请号：US15112429

申请日：2014-03-19

Applicant: Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

Inventor： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/304 ,  H01L2221/68363 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/03 ,  H01L2224/85

Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

Abstract translation: 提供制造半导体器件的方法。 根据该方法，第一胶合层，第一剥离层，第二胶层和第二剥离层可以顺序插入载体和器件晶片之间。 所有第一胶合层，第一释放层，第二胶层和第二剥离层可以由热固性树脂形成。