公开(公告)号：US09153489B2

公开(公告)日：2015-10-06

申请号：US13474992

申请日：2012-05-18

Applicant: Ho-Jin Lee ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025

Abstract: A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Abstract translation: 微电子器件包括：衬底，其具有在其活性表面与其与有源表面相对的非活性表面之间延伸穿过的沟槽;在沟槽的侧壁之间延伸通过衬底的导电通孔电极，以及沿沟槽的非活性表面延伸的绝缘层 衬底在沟槽外部并且至少部分地延伸到沟槽中。 绝缘层限定沟槽中的间隙区域，其分离衬底和通孔电极。 还讨论了相关装置和制造方法。

公开(公告)号：US20140005480A1

公开(公告)日：2014-01-02

申请号：US13922831

申请日：2013-06-20

Applicant: Sebastian Wagner ,  Bernard Dallemagne ,  Hyunsoo Chung

Inventor： Sebastian Wagner ,  Bernard Dallemagne ,  Hyunsoo Chung

IPC: A61B1/00 ,  A61B17/00 ,  A61B1/005

CPC classification number: A61B1/00135 ,  A61B1/00098 ,  A61B1/00137 ,  A61B1/005 ,  A61B1/018 ,  A61B17/00234

Abstract: An endoscope sheath including an elongate flexible hose, which encloses a main lumen, for receiving at least one portion of a shank of a flexible endoscope, and at least one working channel, for receiving at least one portion of a flexible endoscopic working instrument, wherein the endoscope sheath has a transparent distal end portion. Further provided is an endoscope arrangement, and a method for providing an endoscope arrangement.

Abstract translation: 一种内窥镜护套，其包括细长的柔性软管，其包围主腔，用于容纳柔性内窥镜的柄的至少一部分，以及至少一个工作通道，用于容纳柔性内窥镜工作仪器的至少一部分，其中 内窥镜护套具有透明的前端部。 还提供一种内窥镜装置，以及提供内窥镜装置的方法。

公开(公告)号：US08564139B2

公开(公告)日：2013-10-22

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20130134603A1

公开(公告)日：2013-05-30

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20120292782A1

公开(公告)日：2012-11-22

申请号：US13474992

申请日：2012-05-18

Applicant: Ho-Jin LEE ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin LEE ,  Byung Lyul Park ,  SeYoung Jeong ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025

Abstract: A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Abstract translation: 微电子器件包括：衬底，其具有在其活性表面与其与有源表面相对的非活性表面之间延伸穿过的沟槽;在沟槽的侧壁之间延伸通过衬底的导电通孔电极，以及沿沟槽的非活性表面延伸的绝缘层 衬底在沟槽外部并且至少部分地延伸到沟槽中。 绝缘层限定沟槽中的间隙区域，其分离衬底和通孔电极。 还讨论了相关装置和制造方法。

公开(公告)号：US20130210222A1

公开(公告)日：2013-08-15

申请号：US13758239

申请日：2013-02-04

Applicant: Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

Inventor： Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/768 ,  H01L21/02271 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.

Abstract translation: 在一个实施例中，该方法包括在基层中形成导电通孔结构。 基层具有第一表面和第二表面，并且第二表面与第一表面相对。 该方法还包括去除基底层的第二表面以暴露导电通路结构，使得导电通孔结构从第二表面突出，并且在第二表面上形成第一下绝缘层，使得导电通孔的端表面 结构保持由第一下绝缘层暴露。

公开(公告)号：US20150123284A1

公开(公告)日：2015-05-07

申请号：US14470366

申请日：2014-08-27

Applicant: Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

Inventor： Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

公开(公告)号：US09171753B2

公开(公告)日：2015-10-27

申请号：US13758239

申请日：2013-02-04

Applicant: Ho-Jin Lee ,  Kyu-ha Lee ,  Gilheyun Choi ,  YongSoon Choi ,  Pil-Kyu Kang ,  Byung-Lyul Park ,  Hyunsoo Chung

Inventor： Ho-Jin Lee ,  Kyu-ha Lee ,  Gilheyun Choi ,  YongSoon Choi ,  Pil-Kyu Kang ,  Byung-Lyul Park ,  Hyunsoo Chung

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L21/02 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L21/768 ,  H01L21/02271 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.

Abstract translation: 在一个实施例中，该方法包括在基层中形成导电通孔结构。 基层具有第一表面和第二表面，并且第二表面与第一表面相对。 该方法还包括去除基底层的第二表面以暴露导电通路结构，使得导电通孔结构从第二表面突出，并且在第二表面上形成第一下绝缘层，使得导电通孔的端表面 结构保持由第一下绝缘层暴露。

公开(公告)号：US20100190333A1

公开(公告)日：2010-07-29

申请号：US12691780

申请日：2010-01-22

Applicant: Myeong-Soon PARK ,  Eunchul Ahn ,  Hyunsoo Chung ,  Seokho Kim ,  Do-Yeon Choi ,  Jinho Chun

Inventor： Myeong-Soon PARK ,  Eunchul Ahn ,  Hyunsoo Chung ,  Seokho Kim ,  Do-Yeon Choi ,  Jinho Chun

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion.

Abstract translation: 形成连接端子的方法可以包括：准备衬底，在衬底上形成具有开口上部的管状第一导体，在第一导体上形成第二导体，并使第二导体退火， 第二导体通过开口的上部在第一导体的内部空间中延伸。