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    Method and system for virtual metrology in semiconductor manufacturing
    3.
    发明授权
    Method and system for virtual metrology in semiconductor manufacturing 有权
    半导体制造中的虚拟计量方法与系统

    公开(公告)号：US07359759B2

    公开(公告)日：2008-04-15

    申请号：US11378833

    申请日：2006-03-17

    申请人： Chang Yung Cheng ,  Hsueh-Shih Fu ,  Ying-Lang Wang ,  Fan-Tien Cheng

    发明人： Chang Yung Cheng ,  Hsueh-Shih Fu ,  Ying-Lang Wang ,  Fan-Tien Cheng

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41875 ,  G05B2219/32193 ,  G05B2219/45031 ,  Y02P90/22

    摘要： Provided are a method and a system for virtual metrology in semiconductor manufacturing. Process data and metrology data are received. Prediction data is generated based on the process data and metrology data using a learning control model. The system for virtual metrology in a fabrication facility comprises a fault detection and classification system operable to receive process data, a statistical process control system operable to perform statistical process control on a history of physical metrology data to form metrology data, and a virtual metrology application operable to generate prediction data based on the process data and the metrology data using a learning control model.

    摘要翻译： 提供半导体制造中虚拟计量的方法和系统。 接收过程数据和度量数据。 使用学习控制模型，基于过程数据和度量数据生成预测数据。 制造设施中的虚拟计量系统包括可操作以接收过程数据的故障检测和分类系统，可操作以对物理计量数据的历史执行统计过程控制以形成度量数据的统计过程控制系统，以及虚拟计量应用 可操作以使用学习控制模型基于过程数据和度量数据生成预测数据。

    Method and system for virtual metrology in semiconductor manufacturing
    4.
    发明申请
    Method and system for virtual metrology in semiconductor manufacturing 有权
    半导体制造中的虚拟计量方法与系统

    公开(公告)号：US20070100487A1

    公开(公告)日：2007-05-03

    申请号：US11378833

    申请日：2006-03-17

    申请人： Chang Cheng ,  Hsueh-Shih Fu ,  Ying-Lang Wang ,  Fan-Tien Cheng

    发明人： Chang Cheng ,  Hsueh-Shih Fu ,  Ying-Lang Wang ,  Fan-Tien Cheng

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41875 ,  G05B2219/32193 ,  G05B2219/45031 ,  Y02P90/22

    摘要： Provided are a method and a system for virtual metrology in semiconductor manufacturing. Process data and metrology data are received. Prediction data is generated based on the process data and metrology data using a learning control model. The system for virtual metrology in a fabrication facility comprises a fault detection and classification system operable to receive process data, a statistical process control system operable to perform statistical process control on a history of physical metrology data to form metrology data, and a virtual metrology application operable to generate prediction data based on the process data and the metrology data using a learning control model.

    摘要翻译： 提供半导体制造中虚拟计量的方法和系统。 接收过程数据和度量数据。 使用学习控制模型，基于过程数据和度量数据生成预测数据。 制造设施中的虚拟计量系统包括可操作以接收过程数据的故障检测和分类系统，可操作以对物理计量数据的历史执行统计过程控制以形成度量数据的统计过程控制系统，以及虚拟计量应用 可操作以使用学习控制模型基于过程数据和度量数据生成预测数据。

    Sensing product and method of making
    7.
    发明授权
    Sensing product and method of making 有权
    感知产品和制作方法

    公开(公告)号：US09419155B2

    公开(公告)日：2016-08-16

    申请号：US13343922

    申请日：2012-01-05

    申请人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/101 ,  H01L31/18

    CPC分类号： H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

    摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

    摘要翻译： 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

    Method and Apparatus for Backside Illumination Sensor
    8.
    发明申请
    Method and Apparatus for Backside Illumination Sensor 有权
    背面照明传感器的方法和装置

    公开(公告)号：US20130228886A1

    公开(公告)日：2013-09-05

    申请号：US13409924

    申请日：2012-03-01

    申请人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L27/1464 ,  H01L27/14687

    摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

    摘要翻译： 公开了用于背面照明（BSI）图像传感器装置的方法和装置。 在包括感光二极管的基板上形成BSI传感器装置。 衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。 另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    9.
    发明申请
    STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
    应力半导体器件及其制造方法

    公开(公告)号：US20120292639A1

    公开(公告)日：2012-11-22

    申请号：US13111732

    申请日：2011-05-19

    申请人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L29/06 ,  H01L29/24 ,  H01L21/762

    CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

    摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

    摘要翻译： 公开了一种制造半导体器件的半导体器件和方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供衬底并在衬底上形成电介质层。 该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层 活动层

    Via/contact and damascene structures and manufacturing methods thereof
    10.
    发明授权
    Via/contact and damascene structures and manufacturing methods thereof 有权
    通孔/接触和镶嵌结构及其制造方法

    公开(公告)号：US08247322B2

    公开(公告)日：2012-08-21

    申请号：US11680981

    申请日：2007-03-01

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。