公开(公告)号：US09419155B2

公开(公告)日：2016-08-16

申请号：US13343922

申请日：2012-01-05

申请人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L31/0232 ,  H01L31/101 ,  H01L31/18

CPC分类号： H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

摘要翻译： 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

公开(公告)号：US20130126950A1

公开(公告)日：2013-05-23

申请号：US13304235

申请日：2011-11-23

申请人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

公开(公告)号：US08435893B1

公开(公告)日：2013-05-07

申请号：US13304235

申请日：2011-11-23

申请人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/44

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

摘要翻译： 提供一种用于形成半导体器件的系统和方法。 一个实施例包括在硅化物区域和衬底之间的过渡区域上形成衬底上的硅化物区域。 控制硅化物前体材料层的厚度以及退火条件，使得在过渡区域内的一种原子种类的比例比另一种原子种类更大，从而增加过渡区域内的空穴迁移率。

公开(公告)号：US20070252277A1

公开(公告)日：2007-11-01

申请号：US11380666

申请日：2006-04-28

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.

摘要翻译： 半导体器件。 所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及 导电层填充入开口。 本发明还提供一种制造半导体器件的方法。

公开(公告)号：US20070205516A1

公开(公告)日：2007-09-06

申请号：US11364088

申请日：2006-03-01

申请人： Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3146 ,  H01L21/31633 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

摘要翻译： 低k电介质层，半导体器件及其制造方法。 低k电介质层包括夹在两个低k电介质子层之间的硬化子层。 硬化的子层通过利用氢等离子体或惰性气体等离子体轰击下面的低k电介质子层的方法形成。 半导体器件包括覆盖衬底上的蚀刻停止层的低k电介质层，以及电连接到衬底的埋入电介质层和蚀刻停止层中的导电材料。

公开(公告)号：US06769959B2

公开(公告)日：2004-08-03

申请号：US10050314

申请日：2002-01-15

申请人： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

发明人： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

IPC分类号： B24B100

CPC分类号： B24B37/04 ,  B24B57/02

摘要： A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

摘要翻译： 公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。 浆料可以间歇地供应到化学机械抛光装置。 通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光 操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。 因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

公开(公告)号：US06248002B1

公开(公告)日：2001-06-19

申请号：US09421509

申请日：1999-10-20

申请人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

发明人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

IPC分类号： B24B100

CPC分类号： B24B37/042

摘要： A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.

摘要翻译： 一种在抛光晶片表面的过程中防止颗粒杂质在含有钨骨塞的半导体衬底表面积聚的方法。 抛光顺序由三个不同的抛光步骤组成，其中前两个步骤使用硬抛光垫，而第三步在第三次抛光期间使用软抛光垫施加浆料。

公开(公告)号：US07128821B2

公开(公告)日：2006-10-31

申请号：US10761477

申请日：2004-01-20

申请人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： C25D5/34 ,  C25F1/00

CPC分类号： H01L21/76843 ,  B24B37/042 ,  B24B37/046 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25F3/02 ,  H01L21/02068 ,  H01L21/32115 ,  H01L21/76865 ,  H01L21/76873

摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.

摘要翻译： 公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。 该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。 该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

公开(公告)号：US20060055928A1

公开(公告)日：2006-03-16

申请号：US10942554

申请日：2004-09-15

申请人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

发明人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

IPC分类号： G01B11/00

CPC分类号： H01L22/34 ,  G01B21/042

摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

摘要翻译： 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时，激光束撞击目标点并释放到生产中。 如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

公开(公告)号：US20050236181A1

公开(公告)日：2005-10-27

申请号：US10917543

申请日：2004-08-12

申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.

摘要翻译： 公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。 该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。 还公开了具有至少一个无空隙通孔的互连结构。