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公开(公告)号:US11823768B2
公开(公告)日:2023-11-21
申请号:US17401270
申请日:2021-08-12
发明人: Lei Zhu , Jianyong Qin
IPC分类号: G11C7/12 , H03K17/567
CPC分类号: G11C7/12 , H03K17/567
摘要: A drive circuit and a memory chip are provided. The drive circuit includes: an amplification module, working under a first voltage domain; an output module, working under a second voltage domain, a power supply voltage of the second voltage domain being greater than a power supply voltage of the first voltage domain, and an output terminal of the output module being an output terminal of the drive circuit; a connection module, connected to an output terminal of the amplification module and an input terminal of the output module; and a feedback module, an input terminal of the feedback module being connected to the output terminal of the output module, and an output terminal of the feedback module being connected to an input terminal of the amplification module.
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公开(公告)号:US11815927B1
公开(公告)日:2023-11-14
申请号:US17937417
申请日:2022-09-30
发明人: Jianyong Qin
摘要: A bandgap reference circuit includes a feedback transistor, a reference setting circuit, an amplification circuit and an output transistor. A source of the feedback transistor is configured to connect to a first power supply, and a drain of the feedback transistor is configured to connect to a first node. The reference setting circuit includes a first bridge arm and a second bridge arm which are connected in parallel. An inverting input terminal of the amplification circuit is connected to the first bridge arm, and a non-inverting input terminal of the amplification circuit is connected to the second bridge arm. A gate of the output transistor is connected to an output terminal of the amplification circuit, and a source of the output transistor is connected to the first power supply.
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公开(公告)号:US12119067B2
公开(公告)日:2024-10-15
申请号:US17818956
申请日:2022-08-10
发明人: Lei Zhu , Jianyong Qin
IPC分类号: G11C7/00 , G01R31/317 , G11C11/401 , G11C16/10 , G11C16/26 , G11C16/32 , H03K19/21
CPC分类号: G11C16/26 , G01R31/31703 , G11C11/401 , G11C16/10 , G11C16/32 , H03K19/21
摘要: A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.
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公开(公告)号:US11894850B1
公开(公告)日:2024-02-06
申请号:US18180018
申请日:2023-03-07
发明人: Xinxin Zhang , Jianyong Qin
CPC分类号: H03K5/01 , G05F1/567 , H03K2005/00019
摘要: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.
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公开(公告)号:US11703905B1
公开(公告)日:2023-07-18
申请号:US17866682
申请日:2022-07-18
发明人: Jianyong Qin , Jianni Li , Zhonglai Liu
IPC分类号: G06F1/06 , H03K3/86 , H03K5/06 , H03K19/1776 , H03K5/05
CPC分类号: G06F1/06 , H03K3/86 , H03K5/05 , H03K5/06 , H03K19/1776
摘要: A clock generation circuit, equidistant four-phase signal generation method and memory are provided. The circuit includes: a four-phase clock generation circuit for receiving an internal clock signal and complementary clock signal of a memory to which the clock generation circuit belongs, configured to generate a first, second, third and fourth clock signals with the same cycle; a signal delay circuit configured to perform signal delay on the first clock signal, second clock signal, third clock signal and fourth clock signal respectively based on the delay command, herein the delays of the first clock signal, second clock signal, third clock signal and fourth clock signal are different; a signal loading circuit configured to generate a first indication signal and second indication signal; and a test circuit configured to perform a duty cycle test based on the first indication signal and second indication signal to acquire equidistant parallel clock signals.
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