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    Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate
    1.
    发明授权
    Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate 有权
    用于形成在衬底内具有嵌入式电互连的集成电路的集成电路和工艺

    公开(公告)号：US08871635B2

    公开(公告)日：2014-10-28

    申请号：US13466895

    申请日：2012-05-08

    申请人： Chanro Park ,  Errol T. Ryan

    发明人： Chanro Park ,  Errol T. Ryan

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76883 ,  H01L21/76832 ,  H01L21/76834

    摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.

    摘要翻译： 提供了用于形成集成电路的集成电路和工艺。 用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。 通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。 阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。 导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。 嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。 在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

    INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE
    2.
    发明申请
    INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE 有权
    用于形成在基板中嵌入电气互连的集成电路的集成电路和处理

    公开(公告)号：US20130299994A1

    公开(公告)日：2013-11-14

    申请号：US13466895

    申请日：2012-05-08

    申请人： Chanro Park ,  Errol T. Ryan

    发明人： Chanro Park ,  Errol T. Ryan

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76883 ,  H01L21/76832 ,  H01L21/76834

    摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.

    摘要翻译： 提供了用于形成集成电路的集成电路和工艺。 用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。 通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。 阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。 导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。 嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。 在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

    Methods of forming copper-based conductive structures on semiconductor devices
    3.
    发明授权
    Methods of forming copper-based conductive structures on semiconductor devices 有权
    在半导体器件上形成铜基导电结构的方法

    公开(公告)号：US08791014B2

    公开(公告)日：2014-07-29

    申请号：US13422439

    申请日：2012-03-16

    申请人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    发明人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76816

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

    摘要翻译： 本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口，通过绝缘材料层中的开口执行第二蚀刻工艺，该开口暴露一部分 下面的含铜结构，进行湿蚀刻处理以去除图案化的金属硬掩模层，通过绝缘材料层中的开口进行选择性金属沉积工艺，以选择性地在含铜结构上形成金属区域，之后 形成金属区域，在金属区域上方的开口中形成含铜结构体。

    Capacitors, systems, and methods
    6.
    发明授权
    Capacitors, systems, and methods 失效
    电容器，系统和方法

    公开(公告)号：US08432020B2

    公开(公告)日：2013-04-30

    申请号：US12794251

    申请日：2010-06-04

    申请人： Chanro Park ,  Sangduk Park ,  Paul D. Kirsch ,  David Gilmer ,  Chang Yong Kang ,  Joel Barnett

    发明人： Chanro Park ,  Sangduk Park ,  Paul D. Kirsch ,  David Gilmer ,  Chang Yong Kang ,  Joel Barnett

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/40 ,  H01L28/65

    摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

    摘要翻译： 公开了电容器，系统和方法。 在一个实施例中，电容器包括第一电极。 电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。 电容器还可以包括具有邻近第一绝缘体层的负VCC的第二绝缘体层。 电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。 电容器还可以包括与第三绝缘体层相邻的第二电极。

    Mask schemes for patterning magnetic tunnel junctions
    9.
    发明授权
    Mask schemes for patterning magnetic tunnel junctions 失效
    用于图案化磁隧道结的掩模方案

    公开(公告)号：US07001783B2

    公开(公告)日：2006-02-21

    申请号：US10868328

    申请日：2004-06-15

    申请人： Gregory Costrini ,  Frank Findeis ,  Gill Yong Lee ,  Chanro Park

    发明人： Gregory Costrini ,  Frank Findeis ,  Gill Yong Lee ,  Chanro Park

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

    摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.

    摘要翻译： 磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。 一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。 硬掩模的第一种材料是薄的并且包括耐蚀刻材料。 沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。 在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。 可以使用保形或非保形材料作为硬掩模的第二材料。 用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

    METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON SEMICONDUCTOR DEVICES
    10.
    发明申请
    METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON SEMICONDUCTOR DEVICES 有权
    在半导体器件上形成基于铜的导电结构的方法

    公开(公告)号：US20130244422A1

    公开(公告)日：2013-09-19

    申请号：US13422439

    申请日：2012-03-16

    申请人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    发明人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76816

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

    摘要翻译： 本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口，通过绝缘材料层中的开口执行第二蚀刻工艺，该开口暴露一部分 下面的含铜结构，进行湿蚀刻处理以去除图案化的金属硬掩模层，通过绝缘材料层中的开口进行选择性金属沉积工艺，以选择性地在含铜结构上形成金属区域，之后 形成金属区域，在金属区域上方的开口中形成含铜结构体。