公开(公告)号：US20050106856A1

公开(公告)日：2005-05-19

申请号：US10714304

申请日：2003-11-14

申请人： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

发明人： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31695

摘要： A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

摘要翻译： 一种形成双镶嵌开口的方法，包括以下步骤。 提供一种其上形成有上覆的暴露的导电层的结构。 在暴露的导电层上形成电介质层。 在电介质层上形成抗反射涂层。 使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。 至少在导电层的暴露部分上形成保护膜部分。 将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。 沟槽开口和通孔包括双镶嵌开口。

公开(公告)号：US07538025B2

公开(公告)日：2009-05-26

申请号：US10714304

申请日：2003-11-14

申请人： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

发明人： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31695

摘要： A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

摘要翻译： 一种形成双镶嵌开口的方法，包括以下步骤。 提供一种其上形成有上覆的暴露的导电层的结构。 在暴露的导电层上形成电介质层。 在电介质层上形成抗反射涂层。 使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。 至少在导电层的暴露部分上形成保护膜部分。 将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。 沟槽开口和通孔包括双镶嵌开口。

公开(公告)号：US07169701B2

公开(公告)日：2007-01-30

申请号：US10882058

申请日：2004-06-30

申请人： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

发明人： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76801 ,  H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1031

摘要： A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

摘要翻译： 一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在所述有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。

公开(公告)号：US20060003576A1

公开(公告)日：2006-01-05

申请号：US10882058

申请日：2004-06-30

申请人： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

发明人： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76801 ,  H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1031

摘要： A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

摘要翻译： 一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。

公开(公告)号：US09230959B2

公开(公告)日：2016-01-05

申请号：US13314942

申请日：2011-12-08

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

公开(公告)号：US20090095980A1

公开(公告)日：2009-04-16

申请号：US11873156

申请日：2007-10-16

申请人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

发明人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

IPC分类号： H01L29/778 ,  H01L29/786

CPC分类号： H01L29/1033 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

摘要翻译： 半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。 半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

公开(公告)号：US20090035909A1

公开(公告)日：2009-02-05

申请号：US11831098

申请日：2007-07-31

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu ,  Ding-Yuan Chen

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu ,  Ding-Yuan Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.

摘要翻译： 本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。 在第一散热片上形成第一层。 第一层包括第一类型的掺杂剂。 第二类型的掺杂剂被提供到第二鳍。 在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

公开(公告)号：US07341943B2

公开(公告)日：2008-03-11

申请号：US11053018

申请日：2005-02-08

申请人： Chen-Nan Yeh ,  Miao-Ju Hsu ,  Hun-Jan Tao

发明人： Chen-Nan Yeh ,  Miao-Ju Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/321 ,  H01L21/76802

摘要： A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass of 15 or greater. The trace gas adds a sputtering aspect to the plasma cleaning and removes polymeric etch by-products and polymeric and other residuals formed during the deposition of dielectric materials or etch stop layers over the copper surface. An anti-corrosion solvent may be used to passivate the copper surface prior to formation of the dielectric materials or etch stop layers.

摘要翻译： 用于蚀刻后铜清洗的方法使用构成等离子体体积的约3-10％的痕量气体添加剂的氢等离子体来清洁通过蚀刻暴露的铜表面。 痕量气体可以是原子态氮或其原子质量为15以上的物质。 痕量气体在等离子体清洗中增加了溅射方面，并且去除了在铜表面沉积介电材料或蚀刻停止层期间形成的聚合物蚀刻副产物和聚合物和其它残余物。 在形成介电材料或蚀刻停止层之前，可以使用防腐溶剂来钝化铜表面。

公开(公告)号：US20050032355A1

公开(公告)日：2005-02-10

申请号：US10633909

申请日：2003-08-04

申请人： Chen-Nan Yeh ,  Yung-Cheng Lu

发明人： Chen-Nan Yeh ,  Yung-Cheng Lu

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/76804

摘要： A method for forming a dual damascene opening to protect a low-K dielectric insulating layer including providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack layer comprising at least one dielectric insulating layer over the at least one dielectric insulating to seal the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; photolithographically patterning and etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; and, etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.

摘要翻译： 一种用于形成双镶嵌开口以保护低K介电绝缘层的方法，包括提供半导体工艺晶片，其包括通过至少一个介电绝缘层的厚度部分延伸的通孔; 在所述至少一个电介质绝缘体上沉积包括至少一个介电绝缘层的第一介电层堆叠层，以密封所述通孔开口; 包覆沉积包括至少一个电介质层的第二介电层堆叠，以在第一介电层堆叠之上形成硬掩模，并与第一介电层堆叠接触; 通过硬掩模和第一介电层堆叠的厚度进行光刻图案化和蚀刻，以形成覆盖并包围通孔孔的沟槽开口蚀刻图案，同时使通孔开口密封; 并且蚀刻穿过所述至少一个介电绝缘层的厚度部分以形成双镶嵌开口。

公开(公告)号：US09048259B2

公开(公告)日：2015-06-02

申请号：US13562805

申请日：2012-07-31

申请人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

摘要翻译： 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。