公开(公告)号：US08822293B2

公开(公告)日：2014-09-02

申请号：US12048119

申请日：2008-03-13

Applicant: Chen-Hua Yu ,  Yihang Chiu ,  Shu-Tine Yang ,  Jyh-Cherng Sheu ,  Chu-Yun Fu ,  Cheng-Tung Lin

Inventor： Chen-Hua Yu ,  Yihang Chiu ,  Shu-Tine Yang ,  Jyh-Cherng Sheu ,  Chu-Yun Fu ,  Cheng-Tung Lin

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.

Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

公开(公告)号：US08138076B2

公开(公告)日：2012-03-20

申请号：US12118919

申请日：2008-05-12

Applicant: Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

Inventor： Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/3141 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/513 ,  H01L29/517

Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.

Abstract translation: 提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。 通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。 如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。 形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。

公开(公告)号：US07799628B2

公开(公告)日：2010-09-21

申请号：US12354558

申请日：2009-01-15

Applicant: Chung-Shi Liu ,  Hsiang-Yi Wang ,  Cheng-Tung Lin ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Hsiang-Yi Wang ,  Cheng-Tung Lin ,  Chen-Hua Yu

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/78

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅 在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

公开(公告)号：US20100052066A1

公开(公告)日：2010-03-04

申请号：US12424153

申请日：2009-04-15

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Yung-Sheng Chiu ,  Chia-Lin Yu

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Yung-Sheng Chiu ,  Chia-Lin Yu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.

Abstract translation: 公开了一种用于制造用于提供改进的功函数值和热稳定性的半导体器件的半导体器件和方法。 半导体器件包括半导体衬底; 半导体衬底上的界面介电层; 界面介电层上的高k栅介质层; 以及在高k栅极电介质层上方的掺杂导电金属氧化物层。

公开(公告)号：US20070221993A1

公开(公告)日：2007-09-27

申请号：US11389309

申请日：2006-03-27

Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

Abstract: A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.

Abstract translation: 提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层 在栅极区域和半导体器件的有源区中。

公开(公告)号：US08198685B2

公开(公告)日：2012-06-12

申请号：US12343307

申请日：2008-12-23

Applicant: Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

Abstract translation: 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

公开(公告)号：US20110178171A1

公开(公告)日：2011-07-21

申请号：US13008597

申请日：2011-01-18

Applicant: Yi-Lin CHEN ,  Horng-Jyh Harn ,  Shinn-Zong Lin ,  Tzyy-Wen Chiou ,  Cheng-Tung Lin

Inventor： Yi-Lin CHEN ,  Horng-Jyh Harn ,  Shinn-Zong Lin ,  Tzyy-Wen Chiou ,  Cheng-Tung Lin

IPC: A61K31/365 ,  A61P35/00

CPC classification number: A61K31/365

Abstract: A method of inhibiting the cellular proliferation of at least one selected from the group consisting of androgen dependent prostate cancer cells, androgen independent prostate cancer cells, oral cancer cells, liver cancer cells (hepatoma), and gastric cancer cells in a subject is provided, wherein the method comprises administrating to the subject an effective amount of an active component selected from the group consisting of Z form isochaihulactone (Z-K8) of the following formula (I), E form isochaihulactone (E-K8) of the following formula (II), a pharmaceutically acceptable salt of Z-K8 or E-K8, a pharmaceutically acceptable ester of Z-K8 or E-K8, and combinations thereof: and R is H, alkoxy, or aryl. Also provided is a method for manufacturing Z-K8 and E-K8.

Abstract translation: 提供一种抑制受试者中选自雄激素依赖性前列腺癌细胞，雄激素依赖性前列腺癌细胞，口腔癌细胞，肝癌细胞（肝癌）和胃癌细胞的至少一种的细胞增殖的方法， 其中所述方法包括向受试者施用有效量的选自下式（I）的Z型异黄酮（Z-K8），下式的E型异黄酮（E-K8）（ II），Z-K8或E-K8的药学上可接受的盐，Z-K8或E-K8的药学上可接受的酯及其组合：R为H，烷氧基或芳基。 还提供了制造Z-K8和E-K8的方法。

公开(公告)号：US20100221878A1

公开(公告)日：2010-09-02

申请号：US12777937

申请日：2010-05-11

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20100155849A1

公开(公告)日：2010-06-24

申请号：US12343307

申请日：2008-12-23

Applicant: Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

Inventor： Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

Abstract translation: 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

公开(公告)号：US20100151639A1

公开(公告)日：2010-06-17

申请号：US12712518

申请日：2010-02-25

Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

Abstract: Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.

Abstract translation: 提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，栅极结构包括栅极电介质和设置在栅极电介质上的栅电极，在半导体衬底中形成源极/漏极区域 在栅极结构的任一侧，在半导体衬底和栅极结构之上形成金属层，金属层包括难熔金属层或难熔金属化合物层; 在所述金属层上形成合金层; 并进行退火，从而分别在栅极结构和源极/漏极区域上形成金属合金硅化物。