公开(公告)号：US07391788B2

公开(公告)日：2008-06-24

申请号：US10299172

申请日：2002-11-19

申请人： Chenmin Zhang ,  Steve Thomas ,  Randall Stolaruk

发明人： Chenmin Zhang ,  Steve Thomas ,  Randall Stolaruk

IPC分类号： H04L12/40

CPC分类号： H04L12/403 ,  G06F13/4291 ,  H04L12/40

摘要： Aspects of the invention provide a method and system for a communication bus for resetting one or more devices connected to the bus. The transceiver bus (620) may include a single serial data line (616), a single serial clock line (614) and a single reset line (612). A status of a slave device coupled to the transceiver bus (620) may be determined by a master device. Based on the status of the slave device, the master device may execute a forced reset or a normal reset. In a case where a device may be unresponsive, the master device may execute a forced reset. Additionally, in a case where a device is responsive but requires resetting, the master device may execute a normal reset and selectively reset a slave device requiring reset.

摘要翻译： 本发明的方面提供了一种用于重置连接到总线的一个或多个设备的通信总线的方法和系统。 收发机总线（620）可以包括单个串行数据线（616），单个串行时钟线（614）和单个复位线（612）。 耦合到收发器总线（620）的从设备的状态可由主设备确定。 基于从设备的状态，主设备可以执行强制复位或正常复位。 在设备无响应的情况下，主设备可以执行强制重置。 此外，在设备响应但需要重置的情况下，主设备可以执行正常复位并且有选择地复位需要复位的从设备。

公开(公告)号：US20070280396A1

公开(公告)日：2007-12-06

申请号：US11806397

申请日：2007-05-31

申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

IPC分类号： H04L7/00

CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

公开(公告)号：US08909956B2

公开(公告)日：2014-12-09

申请号：US12813265

申请日：2010-06-10

申请人： Zhiqing Zhuang ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani ,  Soheyla Kamal

发明人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/172

摘要： A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

摘要翻译： 包括其相关输入输出（IO）在内的状态机和外部接口总是通电并用于管理芯片功率模式和功率模式转换。 芯片功率模式被定义为RUN，HIBERNATE，POWERDOWN，本发明可能更多。 例如，一旦设备处于HIBERNATE或POWERDOWN模式，除了该控制器状态机之外，IC的电源被减少或完全断开。 本发明的状态机和控制机制响应于一些外部“唤醒事件”，通过其控制接口管理外部电源的状态，将芯片带到RUN模式。 该实现实现了小芯片尺寸和极低的功耗。

公开(公告)号：US20100070659A1

公开(公告)日：2010-03-18

申请号：US12265503

申请日：2008-11-05

申请人： Kenneth Ma ,  Chenmin Zhang ,  Alfonsus Lunardhi ,  Manisha Pandya ,  Shimon Elkayam

发明人： Kenneth Ma ,  Chenmin Zhang ,  Alfonsus Lunardhi ,  Manisha Pandya ,  Shimon Elkayam

IPC分类号： G06F13/00 ,  H02J7/00

CPC分类号： G06F13/385 ,  H02J7/0029 ,  H02J7/0078 ,  H02J2007/0039 ,  H02J2007/0062 ,  Y02D10/14 ,  Y02D10/151

摘要： Aspects of a method and system for operating and/or charging a battery powered USB device based on a USB port type are provided. In this regard, in a USB device comprising a power management IC and a multi-function IC, a port type detection module in the multi-function IC may determine whether the USB device is attached to a standard host port or a charging port. Additionally, a power source in the power management IC, which may supply power to the port type detection module, may be enabled upon attachment of the USB device to a USB port and disabled subsequent to determination of port type. Also, one or more portions and/or functions of the power management IC may be configured based on the determined port type. Similarly, one or more portions and/or functions of the multi-function IC may be enabled or disabled based on the determined port type.

摘要翻译： 提供了一种用于操作和/或充电基于USB端口类型的电池供电的USB设备的方法和系统的方面。 在这方面，在包括电源管理IC和多功能IC的USB设备中，多功能IC中的端口类型检测模块可以确定USB设备是连接到标准主机端口还是充电端口。 此外，可以在将USB设备附接到USB端口并且在确定端口类型之后被禁用，可以在电源管理IC中向端口型检测模块供电的电源。 此外，功率管理IC的一个或多个部分和/或功能可以基于确定的端口类型来配置。 类似地，可以基于所确定的端口类型来启用或禁用多功能IC的一个或多个部分和/或功能。

公开(公告)号：US6163867A

公开(公告)日：2000-12-19

申请号：US141957

申请日：1998-08-28

申请人： John Miller ,  Richard Ortiz ,  Chenmin Zhang

发明人： John Miller ,  Richard Ortiz ,  Chenmin Zhang

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318525

摘要： A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.

摘要翻译： 用于测试集成器件（如印刷电路板上使用的芯片）的方法和系统。 该系统包括芯片上形成的耦合到双向输入/输出焊盘的测试逻辑。 该系统能够通过将来自一对焊盘的一个焊盘的输入测试信号耦合到该对焊盘的第二焊盘的输出来测试输入焊盘，输出焊盘和双向焊盘。 如果从第二衬垫读出的信号对应于期望值，则可以认为衬垫被正确连接。 芯片可以在芯片制造期间的任何阶段进行测试，包括在晶片上形成芯片之后，在晶片上切割晶片之后，以及在封装晶粒以产生芯片之后，以及将芯片附接到印刷电路板之后进行测试。 该系统和方法允许在制造过程中快速和容易地测试焊盘连接性，同时最小化芯片上的额外栅极和迹线的数量。

公开(公告)号：US08989331B2

公开(公告)日：2015-03-24

申请号：US11806397

申请日：2007-05-31

申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

IPC分类号： H04L7/00 ,  H04L7/02 ,  G06F1/12

CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

公开(公告)号：US06226777B1

公开(公告)日：2001-05-01

申请号：US09199712

申请日：1998-11-25

申请人： Chenmin Zhang

发明人： Chenmin Zhang

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： An improved integrated circuit design tool allows the incorporation of minor revisions to a high level register transfer language (RTL) code (netlist) by incorporating within a formal verification tool an engineering change order (ECO) compiler. The addition of the ECO compiler to the formal verification tool eliminates the need to rerun a synthesis tool after minor changes to a revised RTL netlist in order to generate a revised gate (logic) level netlist.

摘要翻译： 改进的集成电路设计工具允许通过在形式验证工具中纳入工程变更订单（ECO）编译器，将较小修订版纳入高级别寄存器传输语言（RTL）代码（网表）。 将ECO编译器添加到形式验证工具中，无需在对修改的RTL网表进行轻微更改后重新运行综合工具，以生成修改后的门（逻辑）级网表。

公开(公告)号：US20100257393A1

公开(公告)日：2010-10-07

申请号：US12813265

申请日：2010-06-10

申请人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Soheyla Kamal ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

发明人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Soheyla Kamal ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/172

摘要： A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

摘要翻译： 包括其相关输入输出（IO）在内的状态机和外部接口总是通电并用于管理芯片功率模式和功率模式转换。 芯片功率模式被定义为RUN，HIBERNATE，POWERDOWN，本发明可能更多。 例如，一旦设备处于HIBERNATE或POWERDOWN模式，除了该控制器状态机之外，IC的电源被减少或完全断开。 本发明的状态机和控制机制响应于一些外部“唤醒事件”，通过其控制接口管理外部电源的状态，将芯片带到RUN模式。 该实现实现了小芯片尺寸和极低的功耗。

公开(公告)号：US07739528B2

公开(公告)日：2010-06-15

申请号：US11495745

申请日：2006-07-31

申请人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Soheyla Kamal, legal representative ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

发明人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/172

摘要： A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

摘要翻译： 包括其相关输入输出（IO）在内的状态机和外部接口总是通电并用于管理芯片功率模式和功率模式转换。 芯片功率模式被定义为RUN，HIBERNATE，POWERDOWN，本发明可能更多。 例如，一旦设备处于HIBERNATE或POWERDOWN模式，除了该控制器状态机之外，IC的电源被减少或完全断开。 本发明的状态机和控制机制响应于一些外部“唤醒事件”，通过其控制接口管理外部电源的状态，将芯片带到RUN模式。 该实现实现了小芯片尺寸和极低的功耗。

公开(公告)号：US20070288778A1

公开(公告)日：2007-12-13

申请号：US11495745

申请日：2006-07-31

申请人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Soheyla Kamal ,  Vinay Kumar Bhasin ,  Lawrence John Madar ,  Chenmin Zhang ,  Vafa James Rakshani

发明人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Soheyla Kamal ,  Vinay Kumar Bhasin ,  Lawrence John Madar ,  Chenmin Zhang ,  Vafa James Rakshani

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/172

摘要： A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

摘要翻译： 包括其相关输入输出（IO）在内的状态机和外部接口总是通电并用于管理芯片功率模式和功率模式转换。 芯片功率模式被定义为RUN，HIBERNATE，POWERDOWN，本发明可能更多。 例如，一旦设备处于HIBERNATE或POWERDOWN模式，除了该控制器状态机之外，IC的电源被减少或完全断开。 本发明的状态机和控制机制响应于一些外部“唤醒事件”，通过其控制接口管理外部电源的状态，将芯片带到RUN模式。 该实现实现了小芯片尺寸和极低的功耗。