公开(公告)号：US5783097A

公开(公告)日：1998-07-21

申请号：US871503

申请日：1997-06-09

申请人： Chi-Shen Lo ,  Chao-Hsin Chang ,  Chia-Hsiang Chen ,  Hsien-Wen Chang ,  Chih-Heng Shen

发明人： Chi-Shen Lo ,  Chao-Hsin Chang ,  Chia-Hsiang Chen ,  Hsien-Wen Chang ,  Chih-Heng Shen

IPC分类号： C03C15/00 ,  H01L21/306 ,  H01L21/00

CPC分类号： H01L21/306 ,  C03C15/00

摘要： A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued. Damage to dielectric material at the flat edge of the wafer, which can cause particles to flake off and become a source of defects in subsequent process steps, in thereby avoided.

摘要翻译： 一个简单的，非关键的，低成本的工艺步骤被添加到集成电路晶片的制造中，以在边缘冲洗已经从电极的圆形边缘去除电介质的脊之后去除留在晶片的平坦边缘处的电介质材料的脊 晶圆。 在晶片上形成诸如旋转玻璃等的电介质层。 然后使用边缘冲洗去除在晶片边缘形成的电介质的脊，然而边缘冲洗不会在晶片的平坦边缘处去除电介质的脊。 在晶片上形成一层光致抗蚀剂，选择性地暴露和显影以形成光致抗蚀剂掩模。 然后将晶片的平坦边缘浸入缓冲氧化物蚀刻中以去除晶片平坦边缘处的电介质材料。 然后剥离光致抗蚀剂掩模，继续处理晶片。 在晶片的平坦边缘处的电介质材料损坏，这可能导致颗粒剥离并成为后续工艺步骤中的缺陷源，从而避免了这种损伤。

公开(公告)号：US5783493A

公开(公告)日：1998-07-21

申请号：US789718

申请日：1997-01-27

申请人： Rann Shyan Yeh ,  Chao-Hsin Chang ,  Hsien-Wen Chang

发明人： Rann Shyan Yeh ,  Chao-Hsin Chang ,  Hsien-Wen Chang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31116 ,  H01L21/76814 ,  H01L21/76826

摘要： The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.

摘要翻译： 本发明提供一种制造层间介电层（ILD）的方法，其在硼磷硅玻璃（BPSG）ILD层的蚀刻之后具有减少的析出物。 含有硼和磷的电介质层沉积在衬底上。 在约800-950℃的温度范围内，在电介质层上进行回流处理。使用反应离子蚀刻将电介质层回蚀刻。 在重要的步骤中，通过等离子体处理对电介质层进行表面处理。 用于表面处理的等离子体源气体是选自Ar，NO 2，N 2和O 2的气体，在约250-400℃的温度范围内，在 在约1mtorr和5托之间，RF功率在约300至400瓦特之间的范围内，并且在约15至80秒的范围内。

公开(公告)号：US06261843B1

公开(公告)日：2001-07-17

申请号：US09208933

申请日：1998-12-10

申请人： Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

发明人： Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

IPC分类号： G01N3100

CPC分类号： G01N17/006 ,  G01N2033/0095 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

摘要翻译： 用于监测集成电路晶片的金属腐蚀敏感性的方法和金属测试图案。 形成具有金属圆阵列以模拟接触区域的测试图案，形成用于模拟电极区域的金属条阵列，以及用于模拟体金属区域的覆盖金属层。 使用缺陷扫描系统测量测试图案的每单位面积的第一数量的缺陷。 然后测试图形晶片首次经受环境应力条件，并再次使用缺陷扫描系统测量测试图案的每单位面积的第二数量的缺陷。 将第二个数字和第一个数字之间的差异与临界数字进行比较。 如果发生过度腐蚀，则在继续处理产品晶片之前校正用于生产晶片的工艺。

公开(公告)号：US5874309A

公开(公告)日：1999-02-23

申请号：US730383

申请日：1996-10-16

申请人： Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

发明人： Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

IPC分类号： G01N17/00 ,  G01N33/00 ,  G01N31/00

CPC分类号： G01N17/006 ,  G01N2033/0095 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

摘要翻译： 用于监测集成电路晶片的金属腐蚀敏感性的方法和金属测试图案。 形成具有金属圆阵列以模拟接触区域的测试图案，形成用于模拟电极区域的金属条阵列，以及用于模拟体金属区域的覆盖金属层。 使用缺陷扫描系统测量测试图案的每单位面积的第一数量的缺陷。 然后测试图形晶片首次经受环境应力条件，并再次使用缺陷扫描系统测量测试图案的每单位面积的第二数量的缺陷。 将第二个数字和第一个数字之间的差异与临界数字进行比较。 如果发生过度腐蚀，则在继续处理产品晶片之前校正用于生产晶片的工艺。

公开(公告)号：US20070042532A1

公开(公告)日：2007-02-22

申请号：US11208102

申请日：2005-08-19

申请人： Jung-Yi Tsai ,  Chao-Hsin Chang ,  Wen-Sze Huang

发明人： Jung-Yi Tsai ,  Chao-Hsin Chang ,  Wen-Sze Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/67271 ,  H01L21/67276 ,  H01L21/67333

摘要： A system of packing for turnkey services. An input port receives first and second wafer lots from a semiconductor manufacturer. The first wafer lot comprises a first number of dies, and the second wafer lot comprises a second number of dies. A packing device loads dies of the first wafer lot in a provided carrier having a preset capacity, and each of the loaded carriers is filled to capacity. A controller determines whether there is a remaining die of the first wafer lot that cannot fill one of the carriers, and directs the packing device to load the remaining dies of the first wafer lot and dies of the second wafer lot sequentially.

摘要翻译： 交钥匙服务包装系统。 输入端口从半导体制造商接收第一和第二晶圆批次。 第一晶片块包括第一数量的管芯，第二晶片块包括第二数量的管芯。 包装装置在具有预设容量的所提供的载体中装载第一晶片批次的管芯，并且将每个加载的载体填充到容量。 控制器确定是否存在不能填充一个载体的第一晶片批次的剩余的芯片，并且引导封装装置依次加载第一晶片批次的剩余模具和第二晶片批次的模具。

公开(公告)号：US06389323B1

公开(公告)日：2002-05-14

申请号：US09426405

申请日：1999-10-25

申请人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

发明人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

IPC分类号： G06F1900

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

摘要翻译： 一种方法和系统提供用于确定在多个制造阶段制造半导体晶片的杀手级的屈服损失分析。 该方法包括以下步骤。 目视检查晶片上的半导体器件，以识别在晶片上制造的裸片上的视觉缺陷的位置，并通过位置维持模具上的视觉缺陷的计数。 检查晶片上的半导体管芯是否确定在每个制造阶段晶片上的缺陷管芯的位置和数量。 计算晶片每个阶段的有缺陷的裸片数量。 计算晶片每个阶段的有缺陷的坏死数。 确定有缺陷的坏死计数除以有缺陷的死亡计数的百分比。 绘制每个制造阶段产量损失百分比和有缺陷坏死率的百分比趋势。 比较图，从分析产量损失曲线与该阶段不良模具百分比的相对趋势分析确定杀手阶段。

公开(公告)号：US06500680B1

公开(公告)日：2002-12-31

申请号：US09933682

申请日：2001-08-20

申请人： Yu-Fong Tai ,  Chun-Yi Tsai ,  Chao-Hsin Chang

发明人： Yu-Fong Tai ,  Chun-Yi Tsai ,  Chao-Hsin Chang

IPC分类号： H01L2100

CPC分类号： G05B19/41865 ,  G05B2219/32248 ,  G05B2219/32263 ,  G05B2219/45026 ,  G05B2219/45031 ,  Y02P90/20

摘要： Within both a system for managing a work-in-process (WIP) workload within a fabrication facility and a method for managing the work-in-process (WIP) workload within the fabrication facility, there is determined from an overall routing sequence for fabricating the work-in-process (WIP) workload within the fabrication facility a series of routing sub-sequences which correspond with a series of service codes. By using the series of service codes for routing the work-in-process (WIP) workload within the fabrication facility there may be realized operational efficiencies when fabricating the work-in-process (WIP) workload within the fabrication facility.

摘要翻译： 在用于管理制造设施内的在制品（WIP）工作负载的系统和用于管理制造设备内的在制品（WIP）工作量的方法中，从用于制造的整体路由序列确定 制造设施内的在制品（WIP）工作量与一系列服务代码相对应的一系列路由子序列。 通过使用一系列服务代码来在制造设施内路由工作中（WIP）工作量，在制造工厂内的在制品（WIP）工作量时可能会实现运行效率。

公开(公告)号：US06308576B1

公开(公告)日：2001-10-30

申请号：US09281339

申请日：1999-03-30

申请人： Renn-Shyan Yeh ,  Der-Fang Huang ,  Tzu-Yu Lin ,  Chao-Hsin Chang

发明人： Renn-Shyan Yeh ,  Der-Fang Huang ,  Tzu-Yu Lin ,  Chao-Hsin Chang

IPC分类号： G01B1116

CPC分类号： G01M9/00 ,  G01N3/567

摘要： A method for determining stress effects, or stress endurance of a film layer coated on a wafer during a scrubber clean process is disclosed. In the method, a wafer having a film layer coated on top is held in a stationary position while a high pressure water jet having a pressure larger than 60 kg/cm2 is scanned across a top surface of the film layer and through a center of the wafer. The total number of stress defects is then counted in the scanning path on top of the film layer as an indication of the stress endurance of the specific coating layer. The invention also discloses a method for scrubber cleaning a wafer surface which is coated with a film layer without causing stress defects in the film by rotating a silicon wafer, which has a film layer coated on top at a suitable rotational speed, and then scanning a water jet across a top surface of the film layer without passing through a center of the wafer. The water pressure utilized for the water jet may be suitably between 50 kg/cm2 and 75 kg/cm2. It is preferred that the water jet does not pass any regions on the top surface of the film layer that is less than 2 mm from the center of the wafer.

摘要翻译： 公开了一种在洗涤器清洁过程中确定在晶片上施加的薄膜层的应力作用或应力耐力的方法。 在该方法中，将具有涂覆在顶部上的膜层的晶片保持在静止位置，同时将具有大于60kg / cm 2的压力的高压水射流扫过膜层的顶表面并穿过该膜层的中心 晶圆。 然后在膜层顶部的扫描路径中计数应力缺陷的总数，作为特定涂层的应力耐久性的指示。 本发明还公开了一种用于洗涤器清洁晶片表面的方法，该晶片表面涂覆有薄膜层，而不会通过旋转硅晶片而导致薄膜中的应力缺陷，该硅晶片具有以合适的转速顶部涂覆的薄膜层，然后扫描 水射流穿过薄膜层的顶表面而不穿过晶片的中心。 用于水射流的水压可适当地在50kg / cm2至75kg / cm2之间。 优选的是，水射流不通过距离晶片中心小于2mm的膜层顶表面上的任何区域。

公开(公告)号：US07003365B1

公开(公告)日：2006-02-21

申请号：US11001769

申请日：2004-12-02

申请人： Wei-Kuo Yen ,  Jen-Lin Chao ,  Wei-Chuan Huang ,  Chao-Hsin Chang

发明人： Wei-Kuo Yen ,  Jen-Lin Chao ,  Wei-Chuan Huang ,  Chao-Hsin Chang

IPC分类号： G06F19/00

CPC分类号： G06Q10/06

摘要： In a foundry that produces a product family a system and method of reserving capacity for a pre-process order includes a plurality of products, a common pre-process operation and a plurality of distinct post-process operations corresponding to the products. When a pre-process order related to the pre-process operation from a customer is received, pre-process capacity and post-process operating capacity are reserved according to the pre-process order, and the pre-process capacity is provided for the pre-process. When a post-process order for a product corresponding to a specific post-process operation in the product family is received before a cutoff date, the reserved post-process operating capacity is provided for the corresponding post-process operation. If no post-process order is received before the cutoff date, the reserved post-process operating capacity is released as remnant supply. Other systems and methods are also provided.

摘要翻译： 在生产产品系列的铸造厂中，为预处理订单预留容量的系统和方法包括多个产品，共同的预处理操作和对应于产品的多个不同的后处理操作。 当接收到与客户的预处理操作相关的预处理订单时，根据预处理顺序保留预处理能力和后处理操作容量，并为预处理提供预处理能力 -处理。 当在截止日期之前收到与产品系列中的特定后处理操作相对应的产品的后处理订单时，为相应的后处理操作提供保留的后处理操作容量。 如果在截止日期之前没有收到后处理订单，则保留的后处理操作容量作为剩余供应被释放。 还提供了其他系统和方法。

公开(公告)号：US5877064A

公开(公告)日：1999-03-02

申请号：US893102

申请日：1997-07-15

申请人： Chao-Hsin Chang ,  Yung-Fa Lin

发明人： Chao-Hsin Chang ,  Yung-Fa Lin

IPC分类号： H01L23/544 ,  H01L21/306

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： The present invention discloses a method for marking a wafer surface with minimized particulate contamination problem and further, the method is compatible with a chemical mechanical polishing method for planarization. An identification mark can be made on the non-patterned side of a wafer by a high energy laser beam either with or without an insulating layer deposited on top of the wafer. The method can also be carried out by first providing an identification mark on a non-patterned surface of the wafer and then, after all fabrication processes have been conducted on the patterned side of the wafer and a planarization process is conducted by a chemical mechanical polishing method, the identification mark on the backside of the wafer can be automatically read and then reproduced on the patterned side of the wafer prior to the shipment of the wafer to a customer or to a packaging facility. The present invention method significantly reduces the particle contamination problem that is frequently caused by laser scribing a silicon surface and furthermore, substantially eliminates the problem that an identification mark becomes illegible after a planarization process by chemical mechanical polishing.

摘要翻译： 本发明公开了一种用最小化的颗粒污染问题来标记晶片表面的方法，并且该方法与用于平坦化的化学机械抛光方法兼容。 可以通过高能量激光束在晶片的非图案化侧上形成识别标记，该激光束具有或不具有沉积在晶片顶部上的绝缘层。 该方法还可以通过首先在晶片的非图案化表面上提供识别标记，然后在晶片的图案化侧进行所有制造工艺之后，通过化学机械抛光进行平坦化处理 方法中，在将晶片装运到客户或包装设备之前，晶片背面的识别标记可以自动读取并在晶片的图案化侧再现。 本发明的方法显着地减少了由激光划线硅表面引起的颗粒污染问题，并且基本上消除了通过化学机械抛光在平坦化处理后识别标记变得难以辨认的问题。