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    Method of removing contaminants from a silicon wafer after chemical-mechanical polishing operation
    1.
    发明授权
    Method of removing contaminants from a silicon wafer after chemical-mechanical polishing operation 有权
    在化学机械抛光操作后从硅晶片去除污染物的方法

    公开(公告)号：US07232752B2

    公开(公告)日：2007-06-19

    申请号：US10603924

    申请日：2003-06-24

    申请人： Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

    发明人： Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

    IPC分类号： H01L21/4763 ,  H01L21/302

    CPC分类号： H01L21/3212 ,  H01L21/02074

    摘要： A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

    摘要翻译： 化学机械抛光（CMP）后从硅晶片去除污染物的方法。 在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后，施加去离子水中的臭氧水溶液以清洁硅晶片，从而去除晶片上的污染物。 或者，在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。 或者，在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。

    Post-CMP removal of surface contaminants from silicon wafer
    2.
    发明授权
    Post-CMP removal of surface contaminants from silicon wafer 有权
    CMP后移除表面污染物

    公开(公告)号：US06696361B2

    公开(公告)日：2004-02-24

    申请号：US09854006

    申请日：2001-05-10

    申请人： Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

    发明人： Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

    IPC分类号： H01L214763

    CPC分类号： H01L21/02074 ,  H01L21/3212

    摘要： A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

    摘要翻译： 化学机械抛光（CMP）后从硅晶片去除污染物的方法。 在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后，施加去离子水中的臭氧水溶液以清洁硅晶片，从而去除晶片上的污染物。 或者，在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。 或者，在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。

    Control system for in-situ feeding back a polish profile
    3.
    发明授权
    Control system for in-situ feeding back a polish profile 失效
    用于原位反馈抛光轮廓的控制系统

    公开(公告)号：US06706140B2

    公开(公告)日：2004-03-16

    申请号：US09682486

    申请日：2001-09-07

    申请人： Chia-Lin Hsu ,  Shao-Chung Hu ,  Teng-Chun Tsai

    发明人： Chia-Lin Hsu ,  Shao-Chung Hu ,  Teng-Chun Tsai

    IPC分类号： B24B4900

    CPC分类号： B24B37/04 ,  B24B49/10 ,  B24B57/02 ,  H01L21/30625

    摘要： A chemical mechanical polishing (CMP) machine has a polish platen, having at least a first ring-shaped region and a second ring-shaped region. A control system for in-situ feeding back a polish profile of the CMP machine has at least a first sensor and a second sensor, respectively installed in the first and the second ring-shaped regions, and a control unit electrically connected to the first sensor and the second sensor for comparing the polish rates of portions of the wafer over the first and the second ring-shaped regions, respectively, according to signals of the first and the second sensors, and adjusting amounts of a slurry supplied by first and second slurry pump valves, corresponding to the first and second ring-shaped regions, according to a predetermined process, or adjusting forces loaded to the first and second regions of the wafer according to the predetermined process.

    摘要翻译： 化学机械抛光（CMP）机器具有抛光台板，具有至少第一环形区域和第二环形区域。 用于原位反馈CMP机的抛光轮廓的控制系统具有分别安装在第一和第二环形区域中的至少第一传感器和第二传感器，以及电连接到第一传感器的控制单元 以及第二传感器，用于根据第一和第二传感器的信号分别比较第一和第二环形区域上的部分晶片的抛光速率，以及调节由第一和第二浆料供应的浆料的量 根据预定过程对应于第一和第二环形区域的泵阀，或根据预定过程加载到晶片的第一和第二区域的调节力。

    METHOD FOR MANUFACTURING THROUGH-SILICON VIA
    4.
    发明申请
    METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
    通过硅制造方法

    公开(公告)号：US20130011938A1

    公开(公告)日：2013-01-10

    申请号：US13176790

    申请日：2011-07-06

    申请人： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    发明人： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

    IPC分类号： H01L21/66 ,  H01L21/306 ,  H01L21/304

    CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

    摘要翻译： 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

    POLY OPENING POLISH PROCESS
    5.
    发明申请
    POLY OPENING POLISH PROCESS 有权

    公开(公告)号：US20120322265A1

    公开(公告)日：2012-12-20

    申请号：US13162776

    申请日：2011-06-17

    申请人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    发明人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC分类号： H01L21/304 ,  H01L21/306

    CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    Method for fabricating a high-density capacitor
    7.
    发明授权
    Method for fabricating a high-density capacitor 有权
    高密度电容器制造方法

    公开(公告)号：US06638830B1

    公开(公告)日：2003-10-28

    申请号：US10065104

    申请日：2002-09-18

    申请人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

    发明人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

    IPC分类号： H01L2120

    CPC分类号： H01L28/91 ,  H01L21/31604 ,  H01L21/3162 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.

    摘要翻译： 一种制造高密度电容器的方法。 至少一个第一沟槽形成在位于半导体衬底上的电介质层中。 在半导体衬底上形成第一衬里层和第一导电层，接着进行第一平面化处理。 在电介质层中形成具有与第一沟槽的接合侧壁的至少一个第二沟槽。 在半导体衬底上形成电容器电介质层，第二衬垫层和第二导电层，接着进行第二平面化处理。 然后将第一导电层和第二导电层的表面暴露以形成具有三维结构的高密度电容器。

    Method of forming embedded capacitor structure applied to logic integrated circuit
    8.
    发明授权
    Method of forming embedded capacitor structure applied to logic integrated circuit 有权
    形成嵌入式电容器结构的方法应用于逻辑集成电路

    公开(公告)号：US06593185B1

    公开(公告)日：2003-07-15

    申请号：US10150385

    申请日：2002-05-17

    申请人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

    发明人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

    IPC分类号： H01L218242

    CPC分类号： H01L27/108 ,  H01L28/90

    摘要： A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

    摘要翻译： 公开了一种用于制造垂直三维金属 - 绝缘体 - 金属电容器（MIM电容器）结构的方法。 本发明在衬底上利用垂直三维MIM电容器结构，以降低逻辑集成电路中MIM电容器的结构面积，并在芯片上的相同电容下对铜双镶嵌工艺进行集成; 因此，可以增加垂直三维电容器的电容密度。 此外，本发明提供一种制造与铜双镶嵌结构的制造兼容的垂直三维MIM电容器结构的方法，使得可以减少在制造过程中的光掩模的数量。