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    Silicided regions for NMOS and PMOS devices
    4.
    发明申请
    Silicided regions for NMOS and PMOS devices 有权
    用于NMOS和PMOS器件的硅化区域

    公开(公告)号：US20070090462A1

    公开(公告)日：2007-04-26

    申请号：US11248555

    申请日：2005-10-12

    申请人： Chii-Ming Wu ,  Chiang-Ming Chuang ,  Chih-Wei Chang

    发明人： Chii-Ming Wu ,  Chiang-Ming Chuang ,  Chih-Wei Chang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.

    摘要翻译： 提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。 通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。 形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。 可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。 此后，源极/漏极区域可以被硅化。

    Silicided regions for NMOS and PMOS devices
    8.
    发明授权
    Silicided regions for NMOS and PMOS devices 有权
    用于NMOS和PMOS器件的硅化区域

    公开(公告)号：US07687861B2

    公开(公告)日：2010-03-30

    申请号：US11248555

    申请日：2005-10-12

    申请人： Chii-Ming Wu ,  Chiang-Ming Chuang ,  Chih-Wei Chang

    发明人： Chii-Ming Wu ,  Chiang-Ming Chuang ,  Chih-Wei Chang

    IPC分类号： H01L27/092

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.

    摘要翻译： 提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。 通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。 形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。 可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。 此后，源极/漏极区域可以被硅化。

    Silicide formation on SiGe
    9.
    发明授权
    Silicide formation on SiGe 有权
    SiGe上的硅化物形成

    公开(公告)号：US07432559B2

    公开(公告)日：2008-10-07

    申请号：US11523683

    申请日：2006-09-19

    申请人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

    发明人： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC分类号： H01L29/40

    CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7848 ,  Y10S438/933

    摘要： A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

    摘要翻译： 半导体结构包括第一含硅层，其包含选自基本上由碳和锗组成的组的元素，其中所述含硅层具有元素与元素和硅的元素的第一原子百分比，第二含硅层包含 第一含硅层上的元素，以及第二含硅层上的硅化物层。 第二含硅层中的元素具有与元素和硅的元素的第二原子百分比，其中第二原子百分比基本上低于第一原子百分比。

    Method for silicide formation on semiconductor devices
    10.
    发明申请
    Method for silicide formation on semiconductor devices 有权
    在半导体器件上形成硅化物的方法

    公开(公告)号：US20070178696A1

    公开(公告)日：2007-08-02

    申请号：US11343648

    申请日：2006-01-30

    申请人： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    发明人： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518

    摘要： A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.

    摘要翻译： 一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。 在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。 冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。 在沉积过程中镍的扩散最小化。 沉积后，使用退火工艺来促使形成均匀的硅化物膜。 在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。